TSI148-133IL IDT, Integrated Device Technology Inc, TSI148-133IL Datasheet - Page 267

• Manufacturer Part Number: TSI148-133IL
• Description: IC PCI-VME BRIDGE 456PBGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Tsi148&Trade;r

Specifications of TSI148-133IL

• Applications: PCI-to-VME Bridge
• Interface: PCI
• Voltage - Supply: 3.3V
• Package / Case: 456-PBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 800-1905

Tsi148 PCI/X-to-VME Bus Bridge User Manual
80A3020_MA001_13
VES (VMEbus Exception Status): This bit is set when the VMEbus exception registers are
updated. The VMEbus error diagnostic registers are updated when the VES bit is clear and the
a VMEbus master transfer is terminated with an error condition, a 2eVME transfer is
terminated by the slave or 2eSST transfer is terminated with the last word invalid. If an
exception occurs and the VES bit is set, then the current status is retained and the VEOF bit is
set. This bit is cleared by writing a one to the VESCL bit.
VEOF (VMEbus Exception Overflow): If the VES bit is clear and a VMEbus exception
occurs, the VMEbus error diagnostic registers capture the VMEbus address and attributes. If
another error occurs and the VES bit is set, then the VEOF bit is set and the registers are not
updated. The VEOF and VES bits are cleared by writing a one to the VESCL bit.
VESCL (VMEbus Exception Status Clear): When this bit is set, the VES and VEOF bits
are cleared. This bit always reads zero and writing a zero has no effect.
2eOT (2e Odd Termination): This bit is set when the error diagnostic registers are updated
because a 2eSST transfer was terminated with a last word invalid exception. This bit is also
set when a 2eVME transfer receives a slave termination or error termination on an odd beat.
This bit is only updated when the VES bit is clear.
2eST (2e Slave Terminated): This bit is set when the error diagnostic registers are updated
because a 2eVME or 2eSST transfer was terminated by the slave. This bit is only updated
when the VES bit is clear.
BERR (VMEbus Error): This bit is set when the error diagnostic registers are updated
because a VMEbus transfer was terminated with an error. This bit is only updated when the
VES bit is clear.
LWORD (LWORD): This bit captures the state of the VMEbus LWORD_ signal when the
Tsi148 is VME Master and an exception occurs. This bit is set when the LWORD_ signal is
asserted.This bit is only updated when the VES bit is clear.
WRITE (WRITE): This bit captures the state of the VMEbus WRITE_ signal when the
Tsi148 is VME Master and an exception occurs. This bit is set when the WRITEI_ signal is
asserted.This bit is only updated when the VES bit is clear.
IACK (IACK): This bit captures the state of the VMEbus IACK_ signal when the Tsi148 is
VME Master and an exception occurs. This bit is set when the IACK_ signal is asserted.This
bit is only updated when the VES bit is clear.
DS1 (DS1): This bit captures the state of the VMEbus DS1_ signal when the Tsi148 is VME
Master and an exception occurs. This bit is set when the DS1I_ signal is asserted. This bit is
only updated when the VES bit is clear.
10. Registers > Register Map
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