ADF7023-JBCPZ Analog Devices Inc, ADF7023-JBCPZ Datasheet - Page 30

• Manufacturer Part Number: ADF7023-JBCPZ
• Description: TXRX FSK/GFSK/MSK/GMSK 32LFCSP
• Manufacturer: Analog Devices Inc
• Series: -r

Specifications of ADF7023-JBCPZ

• Frequency: 902MHz ~ 958MHz
• Data Rate - Maximum: 300kbps
• Modulation Or Protocol: FSK, GFSK, GMSK, MSK
• Applications: ISM
• Power - Output: 13.5dBm
• Sensitivity: -116dBm
• Voltage - Supply: 2.2 V ~ 3.6 V
• Current - Receiving: 12.8mA
• Current - Transmitting: 32.1mA
• Data Interface: PCB, Surface Mount
• Memory Size: -
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-WFQFN Exposed Pad, CSP
• Rf Ic Case Style: LFCSP
• No. Of Pins: 32
• Supply Voltage Range: 2.2V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Transmitting Current: 32.1mA
• Data Rate: 300Kbps
• Modulation Type: 2FSK, GFSK, MSK
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ADF7023-J
COMMANDS
The commands that are supported by the radio controller are
detailed in this section. They initiate transitions between radio
states or perform tasks as indicated in Figure 47. The execution
times for all radio state transitions are detailed in Table 11 and
Table 12.
CMD_PHY_OFF (0xB0)
This command transitions the ADF7023-J to the PHY_OFF
state. It can be issued in the PHY_ON state. It powers down
the RF and VCO regulators.
CMD_PHY_ON (0xB1)
This command transitions the ADF7023-J to the PHY_ON state.
If the command is issued in the PHY_OFF state, it powers up
the RF and VCO regulators and performs an IF filter calibration
if the BB_CAL bit is set in the MODE_CONTROL register
(Address 0x11A).
If the command is issued from the PHY_TX state, the host
processor performs the following procedure:
1.
2.
3.
4.
5.
If the command is issued from the PHY_RX state, the
communications processor performs the following procedure:
1.
2.
3.
4.
5.
CMD_PHY_SLEEP (0xBA)
This command transitions the ADF7023-J to the very low
power PHY_SLEEP state in which the WUC is operational (if
enabled), and the BBRAM contents are retained. It can be issued
from the PHY_OFF or PHY_ON state.
CMD_PHY_RX (0xB2)
This command can be issued in the PHY_ON, PHY_RX, or
PHY_TX state. If the command is issued in the PHY_ON state,
the communications processor performs the following procedure:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Ramps down the PA.
Sets the external PA signal low (if enabled).
Turns off the digital transmit clocks.
Powers down the synthesizer.
Sets FW_STATE = PHY_ON.
Copies the measured RSSI to the RSSI_READBACK register.
Sets the external LNA signal low (if enabled).
Turns off the digital receiver clocks.
Powers down the synthesizer and the receiver circuitry
(ADC, RSSI, IF filter, mixer, and LNA).
Sets FW_STATE = PHY_ON.
Powers up the synthesizer.
Powers up the receiver circuitry (ADC, RSSI, IF filter,
mixer, and LNA).
Sets the RF channel based on the CHANNEL_FREQ[23:0]
setting in BBRAM.
Sets the synthesizer bandwidth.
Does a VCO calibration.
Delays for synthesizer settling.
Enables the digital receiver blocks.
Sets the external LNA enable signal high (if enabled).
Sets FW_STATE = PHY_RX.
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If the command is issued in the PHY_RX state, the communications
processor performs the following procedure:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Sets FW_STATE = PHY_RX.
If the command is issued in the PHY_TX state, the communications
processor performs the following procedure:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Sets the external LNA enable signal high (if enabled).
11. Sets FW_STATE = PHY_RX.
CMD_PHY_TX (0xB5)
This command can be issued in the PHY_ON, PHY_TX, or
PHY_RX state. If the command is issued in the PHY_ON state,
the communications processor performs the following procedure:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Transmits data.
Sets the external LNA signal low (if enabled).
Unlocks the AFC and AGC.
Turns off the receive blocks.
Sets the RF channel based on the CHANNEL_FREQ[23:0]
setting in BBRAM.
Sets the synthesizer bandwidth.
Does a VCO calibration.
Delays for synthesizer settling.
Enables the digital receiver blocks.
Sets the external LNA enable signal high (if enabled).
Ramps down the PA.
Sets the external PA signal low (if enabled).
Turns off the digital transmit blocks.
Powers up the receiver circuitry (ADC, RSSI, IF filter,
mixer, and LNA).
Sets the RF channel based on the CHANNEL_FREQ[23:0]
setting in BBRAM.
Sets the synthesizer bandwidth.
Does a VCO calibration.
Delays for synthesizer settling.
Enables the digital receiver blocks.
Powers up the synthesizer.
Sets the RF channel based on the CHANNEL_FREQ[23:0]
setting in BBRAM.
Sets the synthesizer bandwidth.
Does a VCO calibration.
Delays for synthesizer settling.
Enables the digital transmit blocks.
Sets the external PA enable signal high (if enabled).
Ramps up the PA.
Sets FW_STATE = PHY_TX.