ADF7023-JBCPZ Analog Devices Inc, ADF7023-JBCPZ Datasheet - Page 32

• Manufacturer Part Number: ADF7023-JBCPZ
• Description: TXRX FSK/GFSK/MSK/GMSK 32LFCSP
• Manufacturer: Analog Devices Inc
• Series: -r

Specifications of ADF7023-JBCPZ

• Frequency: 902MHz ~ 958MHz
• Data Rate - Maximum: 300kbps
• Modulation Or Protocol: FSK, GFSK, GMSK, MSK
• Applications: ISM
• Power - Output: 13.5dBm
• Sensitivity: -116dBm
• Voltage - Supply: 2.2 V ~ 3.6 V
• Current - Receiving: 12.8mA
• Current - Transmitting: 32.1mA
• Data Interface: PCB, Surface Mount
• Memory Size: -
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-WFQFN Exposed Pad, CSP
• Rf Ic Case Style: LFCSP
• No. Of Pins: 32
• Supply Voltage Range: 2.2V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Transmitting Current: 32.1mA
• Data Rate: 300Kbps
• Modulation Type: 2FSK, GFSK, MSK
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ADF7023-J
CMD_AES_ENCRYPT (0xD0), CMD_AES_DECRYPT
(0xD2), and CMD_AES_DECRYPT_INIT (0xD1)
These commands allow AES, 128-bit block encryption and
decryption of transmit and receive data using key sizes of
128 bits, 192 bits, or 256 bits.
The AES commands require that the AES firmware module
has been loaded to the ADF7023-J program RAM. The AES
firmware module is available from Analog Devices. See the
Downloadable Firmware Modules section for details on the
AES encryption and decryption module.
CMD_RS_ENCODE_INIT (0xD1), CMD_RS_ENCODE
(0xD0), and CMD_RS_DECODE (0xD2)
These commands perform Reed-Solomon encoding and
decoding of transmit and receive data, thereby allowing
detection and correction of errors in the received packet.
These commands require that the Reed-Solomon firmware
module has been loaded to the ADF7023-J program RAM.
The Reed-Solomon firmware module is available from Analog
Devices. See the Downloadable Firmware Modules section for
details on this module.
AUTOMATIC STATE TRANSITIONS
On certain events, the communications processor can automatically
transition the ADF7023-J between states. These automatic
transitions are illustrated as dashed lines in Figure 47 and are
explained in this section.
TX_EOF
The communications processor automatically transitions the
device from the PHY_TX state to the PHY_ON state at the end
of a packet transmission. On the transition, the communications
processor performs the following actions:
1.
2.
3.
4.
5.
RX_EOF
The communications processor automatically transitions the
device from the PHY_RX state to the PHY_ON state at the end
of a packet reception. On the transition, the communications
processor performs the following actions:
1.
2.
3.
4.
5.
Ramps down the PA.
Sets the external PA signal low.
Disables the digital transmitter blocks.
Powers down the synthesizer.
Sets FW_STATE = PHY_ON.
Copies the measured RSSI to the RSSI_READBACK
register (Address 0x312).
Sets the external LNA signal low.
Disables the digital receiver blocks.
Powers down the synthesizer and the receiver circuitry
(ADC, RSSI, IF filter, mixer, and LNA).
Sets FW_STATE = PHY_ON.
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RX_TO_TX_AUTO_TURNAROUND
If the RX_TO_TX_AUTO_TURNAROUND bit in the MODE_
CONTROL register (Address 0x11A) is enabled, the device
automatically transitions to the PHY_TX state at the end of a
valid packet reception, on the same RF channel frequency. On
the transition, the communications processor performs the
following actions:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Sets the external PA signal high (if enabled).
11. Ramps up the PA.
12. Sets FW_STATE = PHY_TX.
13. Transmits data.
In sport mode, the RX_TO_TX_AUTO_TURNAROUND
transition is disabled.
TX_TO_RX_AUTO_TURNAROUND
If the TX_TO_RX_AUTO_TURNAROUND bit in the MODE_
CONTROL register (Address 0x11A) is enabled, the device
automatically transitions to the PHY_RX state at the end of a
packet transmission, on the same RF channel frequency. On
the transition, the communications processor performs the
following actions:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Enables the digital receiver blocks.
11. Sets the external LNA signal high (if enabled).
12. Sets FW_STATE = PHY_RX.
In sport mode, the TX_TO_RX_AUTO_TURNAROUND
transition is disabled.
WUC Timeout
The ADF7023-J can use the WUC to wake from sleep on a
timeout of the hardware timer. The device wakes into the
PHY_OFF state. See the WUC Mode section for further details.
Sets the external LNA signal low.
Unlocks the AGC and AFC (if enabled).
Disables the digital receiver blocks.
Powers down the receiver circuitry (ADC, RSSI, IF filter,
mixer, and LNA).
Sets RF channel frequency (same as the previous receive
channel frequency).
Sets the synthesizer bandwidth.
Does VCO calibration.
Delays for synthesizer settling.
Enables the digital transmitter blocks.
Ramps down the PA.
Sets the external PA signal low.
Disables the digital transmitter blocks.
Powers up the receiver circuitry (ADC, RSSI, IF filter, mixer,
and LNA).
Sets the RF channel (same as the previous transmit channel
frequency).
Sets the synthesizer bandwidth.
Does VCO calibration.
Delays for synthesizer settling.
Turns on AGC and AFC (if enabled).