ADF7023-JBCPZ Analog Devices Inc, ADF7023-JBCPZ Datasheet - Page 44

• Manufacturer Part Number: ADF7023-JBCPZ
• Description: TXRX FSK/GFSK/MSK/GMSK 32LFCSP
• Manufacturer: Analog Devices Inc
• Series: -r

Specifications of ADF7023-JBCPZ

• Frequency: 902MHz ~ 958MHz
• Data Rate - Maximum: 300kbps
• Modulation Or Protocol: FSK, GFSK, GMSK, MSK
• Applications: ISM
• Power - Output: 13.5dBm
• Sensitivity: -116dBm
• Voltage - Supply: 2.2 V ~ 3.6 V
• Current - Receiving: 12.8mA
• Current - Transmitting: 32.1mA
• Data Interface: PCB, Surface Mount
• Memory Size: -
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-WFQFN Exposed Pad, CSP
• Rf Ic Case Style: LFCSP
• No. Of Pins: 32
• Supply Voltage Range: 2.2V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Transmitting Current: 32.1mA
• Data Rate: 300Kbps
• Modulation Type: 2FSK, GFSK, MSK
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ADF7023-J
INTERRUPT GENERATION
The ADF7023-J uses a highly flexible, powerful interrupt
system with support for MAC level interrupts and PHY level
interrupts. To enable an interrupt source, the corresponding
mask bit must be set. When an enabled interrupt occurs, the
IRQ_GP3 pin goes high, and the interrupt bit of the status word
is set to Logic 1. The host processor can use either the IRQ_GP3
pin or the status word to check for an interrupt. After an
interrupt is asserted, the ADF7023-J continues operations
unaffected, unless it is directed to do otherwise by the host
processor. An outline of the interrupt source and mask system
is shown in Table 23.
MAC interrupts can be enabled by writing a Logic 1 to the relevant
bits of the INTERRUPT_MASK_0 register (Address 0x100) and
PHY level interrupts by writing a Logic 1 to the relevant bits of
the INTERRUPT_MASK_1 register (Address 0x101). The
structure of these memory locations is described in Table 23.
In the case of an interrupt condition, the interrupt source can
be determined by reading the INTERRUPT_SOURCE_0
register (Address 0x336) and the INTERRUPT_SOURCE_1
register (Address 0x337). The bit that corresponds to the
relevant interrupt condition is high. The structure of these two
registers is shown in Table 24.
Table 23. Structure of the Interrupt Mask Registers
Register
INTERRUPT_MASK_0,
Address 0x100
Bit
7
6
5
4
3
2
1
0
Name
INTERRUPT_NUM_WAKEUPS
INTERRUPT_SWM_RSSI_DET
INTERRUPT_AES_DONE
INTERRUPT_TX_EOF
INTERRUPT_ADDRESS_MATCH
INTERRUPT_CRC_CORRECT
INTERRUPT_SYNC_DETECT
INTERRUPT_PREAMBLE_DETECT
Rev. 0 | Page 44 of 100
Description
Interrupt when the number of WUC wake-ups
(NUMBER_OF_WAKEUPS[15:0]) has reached the threshold
(NUMBER_OF_WAKEUPS_IRQ_THRESHOLD[15:0])
1: interrupt enabled; 0: interrupt disabled
Interrupt when the measured RSSI during smart wake mode has
exceeded the RSSI threshold value (SWM_RSSI_THRESH,
Address 0x108)
1: interrupt enabled; 0: interrupt disabled
Interrupt when an AES encryption or decryption command is
complete; available only when the AES firmware module has been
loaded to the ADF7023-J program RAM
1: interrupt enabled; 0: interrupt disabled
Interrupt when a packet has finished transmitting
1: interrupt enabled; 0: interrupt disabled
Interrupt when a received packet has a valid address match
1: interrupt enabled; 0: interrupt disabled
Interrupt when a received packet has the correct CRC
1: interrupt enabled; 0: interrupt disabled
Interrupt when a qualified sync word has been detected in the
received packet
1: interrupt enabled; 0: interrupt disabled
Interrupt when a qualified preamble has been detected in the
received packet
1: interrupt enabled; 0: interrupt disabled
Following an interrupt condition, the host processor should
clear the relevant interrupt flag so that further interrupts assert
the IRQ_GP3 pin. This is performed by writing a Logic 1 to the
bit that is high in either the INTERRUPT_SOURCE_0 or the
INTERRUPT_SOURCE_1 register. If multiple bits in the interrupt
source registers are high, they can be cleared individually or
altogether by writing Logic 1 to them. The IRQ_GP3 pin goes
low when all the interrupt source bits are cleared.
As an example, take the case where a battery alarm (in the
INTERRUPT_SOURCE_1 register) interrupt occurs. The host
processor should do the following:
1.
2.
3.
Read the interrupt source registers. In this example, if none
of the interrupt flags in INTERRUPT_SOURCE_0 are
enabled, only INTERRUPT_SOURCE_1 must be read.
Clear the interrupt by writing 0x80 (or 0xFF) to
INTERRUPT_SOURCE_1.
Respond to the interrupt condition.