ADF7023-JBCPZ Analog Devices Inc, ADF7023-JBCPZ Datasheet - Page 87

• Manufacturer Part Number: ADF7023-JBCPZ
• Description: TXRX FSK/GFSK/MSK/GMSK 32LFCSP
• Manufacturer: Analog Devices Inc
• Series: -r

Specifications of ADF7023-JBCPZ

• Frequency: 902MHz ~ 958MHz
• Data Rate - Maximum: 300kbps
• Modulation Or Protocol: FSK, GFSK, GMSK, MSK
• Applications: ISM
• Power - Output: 13.5dBm
• Sensitivity: -116dBm
• Voltage - Supply: 2.2 V ~ 3.6 V
• Current - Receiving: 12.8mA
• Current - Transmitting: 32.1mA
• Data Interface: PCB, Surface Mount
• Memory Size: -
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-WFQFN Exposed Pad, CSP
• Rf Ic Case Style: LFCSP
• No. Of Pins: 32
• Supply Voltage Range: 2.2V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Transmitting Current: 32.1mA
• Data Rate: 300Kbps
• Modulation Type: 2FSK, GFSK, MSK
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 82. 0x120: SYNC_CONTROL
Bit
[7:6]
[5]
[4:0]
Table 83. 0x121: SYNC_BYTE_0
Bit
[7:0]
Table 84. 0x122: SYNC_BYTE_1
Bit
[7:0]
Table 85. 0x123: SYNC_BYTE_2
Bit
[7:0]
Table 86. 0x124: TX_BASE_ADR
Bit
[7:0]
Table 87. 0x125: RX_BASE_ADR
Bit
[7:0]
Name
SYNC_ERROR_TOL
Reserved
SYNC_WORD_LENGTH
Name
SYNC_BYTE[7:0]
Name
SYNC_BYTE[15:8]
Name
SYNC_BYTE[23:16]
Name
TX_BASE_ADR
Name
RX_BASE_ADR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 0 | Page 87 of 100
Description
Sets the sync word error tolerance in bits.
SYNC_ERROR_TOL
0
1
2
3
Set to 0.
Sets the sync word length in bits; 24 bits is the maximum. Note that the
sync word matching length can be any value up to 24 bits, but the transmitted
sync word pattern is a multiple of eight bits. Therefore, for nonbyte-length
sync words, the transmitted sync pattern should be filled out with the
preamble pattern.
SYNC_WORD_LENGTH
0
1
…
24
Description
Lower byte of the sync word pattern. The sync word pattern is transmitted
most significant bit first starting with SYNC_BYTE_0. For nonbyte-length
sync words, the remainder of the least significant byte should be stuffed
with the preamble. If SYNC_WORD_LENGTH length is >16 bits, SYNC_BYTE_0,
SYNC_BYTE_1, and SYNC_BYTE_2 are all transmitted for a total of 24 bits. If
SYNC_WORD_LENGTH is between 8 and 15, SYNC_BYTE_1 and SYNC_BYTE_2
are transmitted. If SYNC_WORD_LENGTH is between 1 and 7, SYNC_BYTE_2
is transmitted for a total of eight bits. If the SYNC_WORD_LENGTH is 0, no
sync bytes are transmitted.
Description
Middle byte of the sync word pattern
Description
Upper byte of the sync word pattern
Description
Address in packet RAM of the transmit packet. This address indicates to the
communications processor the location of the first byte of the transmit packet.
Description
Address in packet RAM of the receive packet. The communications processor
writes any qualified received packet to packet RAM, starting at this memory
location.
Bit Error Tolerance
0 bit errors allowed.
One bit error allowed.
Two bit errors allowed.
Three bit errors allowed.
Length in Bits
0
1
…
24
ADF7023-J