ADF7023-JBCPZ Analog Devices Inc, ADF7023-JBCPZ Datasheet - Page 42

• Manufacturer Part Number: ADF7023-JBCPZ
• Description: TXRX FSK/GFSK/MSK/GMSK 32LFCSP
• Manufacturer: Analog Devices Inc
• Series: -r

Specifications of ADF7023-JBCPZ

• Frequency: 902MHz ~ 958MHz
• Data Rate - Maximum: 300kbps
• Modulation Or Protocol: FSK, GFSK, GMSK, MSK
• Applications: ISM
• Power - Output: 13.5dBm
• Sensitivity: -116dBm
• Voltage - Supply: 2.2 V ~ 3.6 V
• Current - Receiving: 12.8mA
• Current - Transmitting: 32.1mA
• Data Interface: PCB, Surface Mount
• Memory Size: -
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-WFQFN Exposed Pad, CSP
• Rf Ic Case Style: LFCSP
• No. Of Pins: 32
• Supply Voltage Range: 2.2V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Transmitting Current: 32.1mA
• Data Rate: 300Kbps
• Modulation Type: 2FSK, GFSK, MSK
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ADF7023-J
To convert a user-defined polynomial to the 2-byte value, the
polynomial should be written in binary format. The x
is assumed equal to 1 and is, therefore, discarded. The remaining
16 bits then make up CRC_POLY_0 (most significant byte) and
CRC_POLY_1 (least significant byte). Two examples of setting
common 16-bit CRCs are shown in Table 22.
Table 22. Example Programming of CRC_POLY_0 and
CRC_POLY_1
Polynomial
x
(CRC-16-IBM)
x
x
x
(CRC-16-DNP)
To enable CRC detection on the receiver, with the default CRC or
user-defined 16-bit CRC, CRC_EN in the PACKET_LENGTH_
CONTROL register (Address 0x126) should be set to 1. An
interrupt can be generated on reception of a CRC verified
packet (see the Interrupt Generation section).
COMMUNICATIONS
16
16
11
6
+ x
+ x
+ x
x
10
PROCESSOR
5
15
PA OUTPUT
13
+ x
FW_STATE
+ x
+ x
+ x
TX DATA
8
2
2
+
+ 1
12
+ 1
+
CMD_PHY_TX
Binary Format
1_1000_0000_
0000_0101
1_0011_1101_
0110_0101
CRC_POLY_0
0x80
0x3D
VCO CAL
142µs
300µs
= 0x00 (BUSY)
16
CRC_POLY_1
0x05
0x65
coefficient
Figure 56. Transmit Packet Timing
SYNTH
55µs
RAMP TIME
Rev. 0 | Page 42 of 100
RAMP
PA
~19µs
POSTAMBLE
The communications processor automatically appends two
bytes of postamble to the end of the transmitted packet. Each
byte of the postamble is 0x55. The first byte is transmitted
immediately after the CRC. The PA ramp-down begins
immediately after the first postamble byte. The second byte
is transmitted while the PA is ramping down.
On the receiver, if the received packet is valid, the RSSI is
automatically measured during the first postamble byte, and the
result is stored in the RSSI_READBACK register (Address 0x312).
The RSSI is measured by the communications processor 17 μs
after the last CRC bit.
TRANSMIT PACKET TIMING
The PA ramp timing in relation to the transmit packet data is
described in Figure 56. After the CMD_PHY_TX command is
issued, a VCO calibration is carried out, followed by a delay for
synthesizer settling. The PA ramp follows the synthesizer settling.
After the PA is ramped up to the programmed rate, there is 1-byte
delay before the start of modulation (preamble). At the beginning
of the second byte of postamble, the PA ramps down. The
communications processor then transitions to the PHY_ON state
or the PHY_RX state (if the TX_TO_RX_AUTO_TURNAROUND
is enabled or the CMD_PHY_RX command is issued).
PREAMBLE
WORD
SYNC
PHY_TX
= 0x14 (PHY_TX)
PAYLOAD
CRC
1 BYTE
POSTAMBLE
RAMP
RAMP TIME
PA