ADF7023-JBCPZ Analog Devices Inc, ADF7023-JBCPZ Datasheet - Page 58
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ADF7023-JBCPZ
Manufacturer Part Number
ADF7023-JBCPZ
Description
TXRX FSK/GFSK/MSK/GMSK 32LFCSP
Manufacturer
Analog Devices Inc
Series
-r
Datasheet
1.EVAL-ADF7023-JDB1Z.pdf
(100 pages)
Specifications of ADF7023-JBCPZ
Frequency
902MHz ~ 958MHz
Data Rate - Maximum
300kbps
Modulation Or Protocol
FSK, GFSK, GMSK, MSK
Applications
ISM
Power - Output
13.5dBm
Sensitivity
-116dBm
Voltage - Supply
2.2 V ~ 3.6 V
Current - Receiving
12.8mA
Current - Transmitting
32.1mA
Data Interface
PCB, Surface Mount
Memory Size
-
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
32-WFQFN Exposed Pad, CSP
Rf Ic Case Style
LFCSP
No. Of Pins
32
Supply Voltage Range
2.2V To 3.6V
Operating Temperature Range
-40°C To +85°C
Transmitting Current
32.1mA
Data Rate
300Kbps
Modulation Type
2FSK, GFSK, MSK
Rohs Compliant
Yes
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
ADF7023-J
Smart Wake Mode
In this low power mode, the WUC, firmware timer, and smart
wake mode are employed to periodically listen for packets. To
enable this mode, the WUC and firmware timer should be
configured and smart wake mode (SWM) enabled (the SWM_EN
bit, Address 0x11A) before entering the PHY_SLEEP state. The
WUC_BBRAM_EN bit (Address 0x30D) should be set to 1 to
ensure that the BBRAM is retained. RSSI prequalification can
be optionally enabled (SWM_RSSI_QUAL = 1, Address 0x11A).
When RSSI prequalification is enabled, the ADF7023-J begins
searching for the preamble only if the RSSI measurement is
greater than the user-defined threshold.
The ADF7023-J is in the PHY_RX state for a duration deter-
mined by the RX_DWELL_TIME setting (Address 0x106).
If the ADF7023-J detects the preamble during the receive dwell
time, it searches for the sync word. If the sync word routine is
detected, the ADF7023-J loads the received data to packet RAM
and checks for a CRC and address match, if enabled. If any of
the receive packet interrupts has been set, the ADF7023-J
returns to the PHY_ON state and waits for a host command.
If the ADF7023-J receives preamble detection during the receive
dwell time but the remainder of the received packet extends
beyond the dwell time, the ADF7023-J extends the dwell time
until all of the packet is received or the packet is recognized as
invalid (for example, there is an incorrect sync word).
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This low power mode terminates when a valid packet interrupt
is received. Alternatively, this low power mode can be terminated
via a firmware timer timeout. This can be useful if certain radio
tasks (for example, IR calibration) or processor tasks must be
run periodically while in the low power mode.
The operation of this low power mode is illustrated in Figure 73.
Exiting Low Power Mode
As described in Figure 69, the ADF7023-J waits for a host
command on any of the termination conditions of the low power
mode. It is also possible to perform an asynchronous exit from
low power mode using the following procedure:
1.
2.
The host processor should then follow the initialization
procedure after a CMD_HW_RESET command, as described in
the Initialization section.
Bring the CS pin of the SPI low and wait until the MISO
output goes high.
Issue a CMD_HW_RESET command.