ADF7023-JBCPZ Analog Devices Inc, ADF7023-JBCPZ Datasheet - Page 64

• Manufacturer Part Number: ADF7023-JBCPZ
• Description: TXRX FSK/GFSK/MSK/GMSK 32LFCSP
• Manufacturer: Analog Devices Inc
• Series: -r

Specifications of ADF7023-JBCPZ

• Frequency: 902MHz ~ 958MHz
• Data Rate - Maximum: 300kbps
• Modulation Or Protocol: FSK, GFSK, GMSK, MSK
• Applications: ISM
• Power - Output: 13.5dBm
• Sensitivity: -116dBm
• Voltage - Supply: 2.2 V ~ 3.6 V
• Current - Receiving: 12.8mA
• Current - Transmitting: 32.1mA
• Data Interface: PCB, Surface Mount
• Memory Size: -
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-WFQFN Exposed Pad, CSP
• Rf Ic Case Style: LFCSP
• No. Of Pins: 32
• Supply Voltage Range: 2.2V To 3.6V
• Operating Temperature Range: -40°C To +85°C
• Transmitting Current: 32.1mA
• Data Rate: 300Kbps
• Modulation Type: 2FSK, GFSK, MSK
• Rohs Compliant: Yes
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ADF7023-J
RADIO BLOCKS
FREQUENCY SYNTHESIZER
A fully integrated RF frequency synthesizer is used to generate
both the transmit signal and the receiver’s local oscillator (LO)
signal. The architecture of the frequency synthesizer is shown in
Figure 78.
The receiver uses a fractional-N frequency synthesizer to generate
the mixer’s LO for down conversion to the intermediate frequency
(IF) of 200 kHz or 300 kHz. In transmit mode, a high resolution
sigma-delta (Σ-Δ) modulator is used to generate the required
frequency deviations at the RF output when FSK data is trans-
mitted. To reduce the occupied FSK bandwidth, the transmitted
bit stream can be filtered using a digital Gaussian filter, which is
enabled via the RADIO_CFG_9 register (Address 0x115). The
Gaussian filter uses a bandwidth time (BT) of 0.5.
The VCO and the PLL loop filter of the ADF7023-J are fully
integrated. To reduce the effect of pulling of the VCO by the
power-up of the PA and to minimize spurious emissions, the
VCO operates at twice the RF frequency. The VCO signal is
then divided by 2, giving the required frequency for the
transmitter and the required LO frequency for the receiver.
A high speed, fully automatic calibration scheme is used to
ensure that the frequency and amplitude characteristics of the
VCO are maintained over temperature, supply voltage, and
process variations.
The calibration is automatically performed when the
CMD_PHY_RX or the CMD_PHY_TX command is
issued. The calibration duration is 142 μs, and if required,
the CALIBRATION_STATUS register (Address 0x339) can be
polled to indicate the completion of the VCO self calibration.
After the VCO is calibrated, the frequency synthesizer settles
to within ±5 ppm of the target frequency in 56 μs.
DATA
26MHz
TX
REF
GAUSSIAN
FILTER
PFD
Figure 78. RF Frequency Synthesizer Architecture
F_DEVIATION
FRAC-N
CHARGE
PUMP
Σ-∆ DIVIDER
FILTER
LOOP
INTEGER-N
N DIVIDER
CALIBRATION
VCO
VCO
÷2
÷2
RF
FREQ
Rev. 0 | Page 64 of 100
Synthesizer Bandwidth
The synthesizer loop filter is fully integrated on chip and has a
programmable bandwidth. The communications processor
automatically sets the bandwidth of the synthesizer when the device
enters the PHY_TX or the PHY_RX state. Upon entering the
PHY_TX state, the communications processor chooses the band-
width based on the programmed modulation scheme (2FSK or
GFSK) and the data rate. This ensures optimum modulation quality
for each data rate. Upon entering the PHY_RX state, the
communications processor sets a narrow bandwidth to ensure best
receiver rejection. In all, there are eight bandwidth configurations.
Each synthesizer bandwidth setting is described in Table 30.
Table 30. Automatic Synthesizer Bandwidth Selections
Description
Rx 2FSK/GFSK/MSK/GMSK
Tx 2FSK/GFSK/MSK/GMSK
Tx 2FSK/GFSK/MSK/GMSK
Tx 2FSK/GFSK/MSK/GMSK
Tx 2FSK/GFSK/MSK/GMSK
Tx 2FSK/GFSK/MSK/GMSK
Tx 2FSK/GFSK/MSK/GMSK
For performance margin to the T96 specification limits, the PLL
closed-loop bandwidth is optimized depending on the data rate.
The following procedure must be used to program the device
for optimized PLL bandwidth settings during transmit operation.
As part of the initial BBRAM configuration, do the following:
•
•
The custom transmit LUT must be written to the 0x010 to 0x018
packet RAM locations. This is achieved using a SPI_MEM_WR
command and a block write as described in the Memory Access
section. The LUT values are described in Table 31.
These values are retained in memory while VDDBAT remains
valid, unless PHY_SLEEP is entered; in which case, the values
must be reprogrammed.
Table 31. T96 Custom Transmit Look-Up Table (LUT)
Register
0x010
0x011
0x012
0x013
0x014
0x015
0x016
0x017
0x018
Issue the SPI_MEM_WR command, writing 0x2 to Bits[5:4]
of Register 0x113 (RADIO_CFG_7).
Issue the CMD_CONFIG_DEV command.
Data Rate = 50 kbps or
100 kbps (CLBW = 130 kHz)
0x10
0x10
0x0F
0x0F
0x1F
0x0F
0x1F
0x33
0x22
Data Rate
(kbps)
All
1 to 49.5
49.6 to 99.1
99.2 to 129.5
129.6 to 179.1
179.2 to 239.9
240 to 300
Data Rate = 200 kbps
(CLBW = 223 kHz)
0x20
0x20
0x0F
0x0F
0x1F
0x05
0x1F
0x33
0x18
Closed-Loop
Synthesizer
Bandwidth (kHz)
92
130
174
174
226
305
382