TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 107

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

7.3.5
Upper Address
Lower Address
7.3.5.1
7.3.5.2
Upper Address
Lower Address
ADDR Bit
ADDR Bit
Data Bus Size
data bus width is selected using the BSZ field of the Channel Control Register (EBCCRn). The address
bits output to each bit of the ADDR[19:0] signal change according to the mode. When access of a size
larger than the data bus width is performed, the dynamic bus sizing function is used to execute multiple
bus access cycles in order from the lower address.
The External Bus Controller supports devices with a data bus width of 8 bits, 16 bits, and 32 bits. The
32-bit Bus Width Mode
which are the upper address, are multiplexed to external ADDR[19:12]. The maximum memory
size is 1 GB.
executed only once on the external bus. 32-bit access is executed twice when performing 1-
double-word access. When a Burst cycle is executed, two 32-bit cycles are executed for each Burst
access when the Bus cycle tries to request a byte combination other than double-word data.
16-bit Bus Width Mode
which are the upper address, are multiplexed to external ADDR[19:12]. In other words, the
address is shifted up one bit relative to the 32-bit bus mode when output. As a result, the
maximum memory size of the 16-bit bus mode is 512 MB.
executed only once on the external bus. 16-bit access is executed twice when performing 1-word
access. 16-bit access is executed four times when performing 1-double-word access. When a Burst
cycle is executed, four 16-bit cycles are executed for each Burst access when the Bus cycle tries to
request a byte combination other than double-word data.
Table 7.3.4 Address Output Bit Correspondence in the 32-bit Mode
Table 7.3.5 Address Output Bit Correspondence in the 16-bit Mode
DATA[31:0] becomes valid.
Bits [21:2] of the physical address are output to ADDR[19:0]. The internal address bits [29:22],
When a Single cycle that accesses 1-Byte/1 half-word/1-word data is executed, 32-bit access is
DATA[15:0] becomes valid.
Bits [20:1] of the physical address are output to ADDR[19:0]. The internal address bits [28:21],
When a Single cycle that accesses 1-Byte or 1 half-word data is executed, 16-bit access is
19 18 17 16 15 14 13 12 11 10 9
19 18 17 16 15 14 13 12 11 10 9
28 27 26 25 24 23 22 21
20 19 18 17 16 15 14 13 12 11 10 9
29 28 27 26 25 24 23 22
21 20 19 18 17 16 15 14 13 12 11 10
7-7
Chapter 7 External Bus Controller
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