TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 418

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

14.3.6.4 DMA Operation
sample-data, it issues a DMA request. When DMAC acknowledges the request by performing
write- or read-access to the ACLC sample-data register, ACLC deasserts the request. Therefore,
the software must properly set up DMAC so that the source or destination points to the
corresponding sample-data register for the DMA channel.
Output/Surround/Center/LFE/Modem Output Register (ACAUDO/SURR/CENT/LFE/
MODODAT) to the DMAC destination address register (DMDARn). For a reception channel,
assign the address of ACLC Audio input/Modem Input Register (ACAUDI/MODIDAT) to the
DMAC source address register (DMSARn).
corresponding sample-data register is accessed. Just unsetting ACLC Control Enable Register
(ACCTLEN)’s DMA Enable (xxxxDMA) bit corresponding to the DMA will not clear the REQ
latch.
operation follows the DMAC specification. Refer to section 8.3.10 for this respect.
Note: Use this setting when DMA chain operation is utilized
When ACLC’s REQ latch (refer to Figure 14.3.6 and Figure 14.3.7) needs to read or write
Setup the DMA Channel Control Registers (DMCCRn) in DMAC as follows.
Immediate chain
DMA request polarity
DMA acknowledge polarity
Request sense
Sample chain
Transfer size
Transfer address mode
For a transmission channel, assign the address of ACLC Audio PCM
When any DMA request is pending, the REQ latch will not deasserted the request until the
The procedure to continuously push or pull the sample-data stream through the chain DMA
14-12
Enable
Low-active
Low-active
Level-sensitive
1 word
1 word
Dual
Chapter 14 AC-link Controller
DMCCRn.IMMCHN = 1 [Note]
DMCCRn.REQPOL = 0
DMCCRn.ACKPOL = 0
DMCCRn.EGREQ = 0
DMCCRn.SMPCHN = 1
DMCCRn.XFSZ = 010b
DMCCRn.SNGAD = 0