TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 272

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

10.3.9
10.3.9.1 Power Management State
using the PCI Bus Reset Signal assertion detection device that the system provides. Then, the software
reset the PCI Controller. The software uses a hardware reset (PCICCFG.HRST) of the PCI Controller
Configuration Register to reset the PCI Controller.
Power Management
Power Management Interface Specifications Version 1.1.
Satellite device. Also, the PCI Satellite device uses the PME* signal to report requests for changing the
power management state or to report to the PCI Host device that a power management event has
occurred.
PCI Reset is detected by either using the PCI Bus Reset Signal as the TX4937 overall reset signal or
The TX4937 PCI Controller supports power management functions that are compliant to PCI Bus
The PCI Host device controls the system status by reporting the power management state to the PCI
management states are defined from State D0 to State D3. The TX4937 supports states D0 through
D3. Figure 10.3.7 illustrates the power management state transition.
management state becomes uninitialized D0. If initialized by the system software at this point, the
state transitions to D0 Active.
Management Control Status Register (PMCSR) of the Configuration space when in the Satellite
mode, then the Power Management State Change bit (P2GSTATUS.PMSC) of the P2G Status
Register is set and transitions to the D3
Change interrupts. The PowerState field value can be read from the PowerState field
(PCISSTATUS.PS) of the Satellite Mode PCI Status Register.
In the case of the PCI Bus Power Management Interface Specifications, four power
After Power On Reset, or when transitioning from the D3
If an external PCI Host device writes 11b (D3
The TX4937 uses the software to change the system status after a status change is detected.
Figure 10.3.7 Transition of the Power Management States
Initialization by the
System Software
D0 Active
Power On Reset
(RESET*
Change PMCSR
PowerState
* )
10-14
Uninitialized
HOT
D0
state. It then becomes possible to report Power State
D3
HOT
Software Reset
hot
) to the PowerState field of the Power
Chapter 10 PCI Controller
HOT
PCI
(RESET
state to the D0 state, the power
RST*
VCCCut-off
* )
*
*
D3
cold