TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 268

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

10.3.5
0xFF_FFFF_FFFF
0x00_FFFF_FFFF
0x00_0000_0000
Target Access (PCI Bus → G-Bus Address Conversion)
converted into a G-Bus address and is used to issue a Bus transaction on the G-Bus. 40-bit PCI Bus
addresses are used on the PCI Bus. Also, 36-bit physical addresses are used on the G-Bus.
10.3.5). The size of each window is fixed. When Bus transactions to these access windows is issued on
the PCI Bus, these Bus transactions are accepted as PCI target devices. The PCI Bus Address is
converted into G-Bus addresses, then Bus transactions are issued to the G-Bus.
window responds to the PCI I/O space access command.
Note: Byte swapping is always disabled when prefetch mode is disabled. When the G-Bus is
During PCI target access, the PCI Bus address of the Bus transaction issued by the PCI Bus is
Three memory access windows and one I/O access window can be set in the PCI bus space (Figure
The memory space window responds to the PCI memory space access command. The I/O space
Memory Space 0
Memory Space 1
Memory Space 2
I/O Space
BusMasterEnable:
Host mode:
Satellite mode: Command Register Bus Master bit
configured for big-endian mode, the order of bits in a 32-bit word does not change
during a PCI transfer. (The byte ordering changes.)
PCI I/O Space
Table 10.3.3 Initiator Access Space Properties Register
Figure 10.3.5 Target Access Memory Window
BusMasterEnable & PCICCFG.G2PM0EN
BusMasterEnable & PCICCFG.G2PM1EN
BusMasterEnable & PCICCFG.G2PM2EN
BusMasterEnable & PCICCFG.G2PIOEN
Memory Access Window
I/O Access Window
PCI State Command Register Bus Master Bit (PCISTATUS.BM)
0xF_FFFF_FFFF
0x0_0000_0000
Enable
10-10
G-Bus Space
Chapter 10 PCI Controller
G2PM0GBASE.BSWAP
G2PM1GBASE.BSWAP
G2PM2GBASE.BSWAP
G2PIOGBASE.BSWAP
0xFF_FFFF_FFFF
0x00_FFFF_FFFF
0x00_0000_0000
Word Swap
PCI Memory Space