TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 177

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

8.3.12
8.3.13
Interrupts
there are completion interrupts for when transfer ends normally and error interrupts for when transfer
ends abnormally for each channel. When an interrupt occurs, then the bit that corresponds to either the
Normal Interrupt Status field (DIS[3:0]) or the Error Interrupt Status field (EIS[3:0]) of the DMA
Master Control Register (DMMCR) is set.
cause. Refer to the explanation for each Status bit for more information regarding each information
cause.
Transfer Stall Detection Function
bus access is performed exceeds the Transfer Stall Detection Interval field (STLTIME) of the DMA
Channel Control Register (DMCCRn), the Transfer Stall Detection bit (STLXFER) of the DMA
Channel Status Register (DMCSRn) is set. An error interrupt is signalled if the Error Interrupt Enable
bit (DMCCRn.INTENE) is set.
bus ownership can be obtained. Furthermore, clearing the Transfer Stall Detection field (STLXFER)
resumes transfer stall detection as well.
Detection function.
An interrupt number (10 – 13) of the Interrupt Controller is mapped to each channel. In addition,
Figure 8.3.6 shows the relationship between the Status bit and Interrupt Enable bit for each interrupt
If the period from when a certain channel last performs internal bus access to when the next internal
In contrast to other error interrupts, DMA transfer is not stopped. Normal DMA transfer is executed if
Setting the Transfer Stall Detection Interval field (STLTIME) to “000” disables the Transfer Stall
DMCSRn.NCHNC
DMCSRn.NTRNFC
DMCSRn.STLXFER
DMCSRn.CFERR
DMCSRn.CHERR
DMCSRn.DESERR
DMCSRn.SORERR
Figure 8.3.6 DMA Controller Interrupt Signal
DMCCRn.INTENC
DMCCRn.INTENT
DMCSRn.ABCHC
8-21
DMCCRn.INTENE
Chapter 8 DMA Controller
DMMCR.DIS[n]
DMMCR.EIS[n]
Interrupt Controller
(Interrupt No. 10 – 13)