TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 70

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

4.2
4.2.1
4.2.2
Register Map
Addressing
physical address 0xF_FF1F_0000 or pointed address by RAMP register (refer to 5.2.7). Figure 4.2.1
shows how to generate internal register address. Physical address 1 and physical address 2 shown
Figure 4.2.1 access the same register.
mapped to the virtual address form 0xFF00_0000 to 0xFF3F_FFFF (32 bit mode) /form
0xFFFF_FFFF_FF00_0000 to 0xFFFF_FFFF_FF3F_FFFF (64 bit mode).
initialization.
Ways to Access to Internal Registers
Second is 64-bit register access. Last is PCI configuration register access in PCI satellite mode.
mode, 32-bit size access is performed shown as Table 4.2.1.
Explanation”), PCI configuration registers are to be accessed through PCI bus in configuration cycles. It
is possible to access to the arbitrary size of PCI configuration register as always Little Endian space
regardless the system setup.
(######## means 32 bits data (upper 32 bits or lower 32 bits) which are accessed.)
TX4937 internal registers are to be accessed through 64 K bytes address space that is based on
In TX49/H3 Core, the physical address form 0xF_FF00_0000 to 0xF_FF3F_FFFF are uncached
This space includes the region form 0xF_FF1F_0000 allocated TX4937 internal registers at
3 ways to access to the internal registers of TX4937 are supported. First is 32-bit register access.
32-bit register supports 32-bit size access only. Another size access without 32-bit size is undefined.
64-bit register supports both 64-bit size access and two times 32-bit size access. In each Endian
When the build-in PCI controller works in the satellite mode (refer to “10.3.1 Terminology
Base Address Register
(0xF_FF1F_0000)
0x*_****_***C
0x*_****_***0
0x*_****_***8
0x*_****_***4
Figure 4.2.1 Generating Physical Address for a Internal Register
Base Address
Address
(RAMP)
Table 4.2.1 32-bit Size Access to 64-bit Register
[63........32] [31........0]
[63........32] [31........0]
########
(Bit which are accessed)
+
+
Big Endian
########
Offset Address
Offset Address
4-2
Chapter 4 Address Mapping
[63........32] [31........0]
[63........32] [31........0]
########
=
=
(Bit which are accessed)
Little Endian
########
Physical Address 1
Physical Address 2