TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 164

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

8.3.4
Internal I/O DMA Transfer Mode
Channel Control Register (DMCCRn) as follows.
•
•
“14.3.6.4 DMA operation (AC-link Controller) for more information.
Performs DMA with the on-chip Serial I/O Controller and the AC-link Controller. Set the DMA
Refer to “8.3.8 Dual Address Transfer” and “11.3.6 DMA transfer (Serial I/O Controller)” or
DMCCRn.EXTRQ = 1: I/O DMA Transfer mode
DMCCRn.SNGAD = 0: Dual Address Transfer
DMAACK[n] signal for the last data transfer in a DMA transfer specified by the current DMA
Channel Register is asserted. Namely, if the Link List Command chain is used, there is one
assertion at the end of each data transfer specified by each Descriptor.
DMA transfer can be set to end normally when the external device asserts the DMADONE* signal
when the DMAACK[n] signal of channel n is asserted. DMADONE* is asserted during
DMAACK[n] is not asserted, then unexpected operation occurs. When DMA transfer is
terminated by the DMADONE* assertion of the external device, the External DONE Assert bit
(DMCSRn.EXTDN) of the DMA Channel Status Register is set regardless of the setting of the
Chain End bit (CHDN) of the DMA Channel Control Register (DMCCRn). Operation is as
follows depending on the setting of the Chain End bit (CHDN).
time, the Normal Chain End bit (NCHNC) and the Normal Transfer End bit (NTRNFC) of the
DMA Channel Status Register are both set and the Transfer Active bit (DMCCRn.XFACT) of the
DMA Channel Control Register is cleared.
Channel Register ends normally, and only the Normal Transfer End bit (NTRNFC) is set. When
the Chain Enable bit (CHNEN) of the DMA Channel Control Register (DMCCRn) is set, chain
transfer is executed and DMA transfer continues. When the Chain Enable bit (CHNEN) is cleared,
the Transfer Active bit (DMCCRn.XFACT) is cleared and the Normal Chain End bit (NCHNC) is
set.
of new DMA access. Operation will not stop even if the bus operation in progress is a Single
transfer or a Burst transfer. For example, if the DMADONE* signal is asserted during Read
operation of Dual Address transfer, the corresponding Write bus operation will also be executed.
(DMCCRn.DNCTRL = “11”), the DMADONE* signal becomes an open drain signal when the
channel becomes active. When used by this mode, the DMADONE* signal must be pulled up by
an external source. When in this mode, the External DONE Assert bit (DMCSRn.EXTDN) is not
only set when asserted by an external device, but is also set when asserted by the TX4937.
When the Chain End bit (CHDN) is cleared, the DMADONE* signal is asserted when the
If the DMADONE* signal is set to be used as an input signal (DMCCRn.DNCTRL = 01/11),
When the Chain End bit (CHDN) is set, all DMA transfer for that chain is terminated. At this
When the Chain End bit (CHDN) is cleared, only DMA transfer specified by the current DMA
Three clock cycles are required from external assertion of the DMADONE* signal to disabling
If the DMADONE* pin is set to become both input and output for channel n
8-8
Chapter 8 DMA Controller