TMPR4937XBG-300 Toshiba, TMPR4937XBG-300 Datasheet - Page 394

• Manufacturer Part Number: TMPR4937XBG-300
• Manufacturer: Toshiba

Specifications of TMPR4937XBG-300

• Family Name: TX49
• Device Core Size: 64b
• Frequency (max): 300MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5V
• Operating Supply Voltage (max): 1.6V
• Operating Supply Voltage (min): 1.4V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: BGA
• Lead Free Status / Rohs Status: Compliant

31:8
Bit
1:0
31
15
7
6
5
4
3
2
12.4.1
Mnemonic
TMODE
CCDE
ECES
CRE
CCS
TCE
Timer Control Register n (TMTCRn)
Reserved
Timer Counter
Enable
Counter Clock
Divider Enable
Counter Reset
Enable
Reserved
External Clock
Edge Select
Counter Clock
Select
Timer Mode
Field Name
Reserved
Timer Count Enable (Default: 0)
This field controls whether the counter runs or stops.
When in the Watchdog mode, counter operation only stops when the
Watchdog Timer Disable bit (TMWTMR2.WDIS) of the Watchdog Timer
Mode Register is set. When the Watchdog Timer Disable bit is cleared, the
value of this Timer Count Enable bit becomes “0”, but the count continues.
0: Stop counter (the counter is also cleared to “0” when CRE = 1)
1: Counter operation
Counter Clock Divide Enable (Default: 0)
This bit enables the divide operation of the internal clock (IMBUSCLK).
The counter stops if this bit is set to “0” when the internal bus clock is in
use.
0: Disable
1: Enable
Counter Reset Enable (Default: 0)
This bit controls the counter reset when the TCE bit was used to stop the
counter.
1: Stop and reset the counter to “0” when the TCE bit is cleared to “0”.
0: Only stop the counter when the TCE bit is cleared to “0”.
During CRE = 1, reset the counter if TCE is set from 1 to 0.
During TCE = 0, the counter isn’t reset if CRE is set from 0 to 1.
When TCE = 1 and CRE = 0, stop and reset the counter if TCE is set to 0
and CRE is set to 1 simultaneously.
External Clock Edge Select (Default: 0)
This bit specifies the counter operation edge when using the counter input
signal (TCLK).
0: Falling edge of the counter input signal (TCLK)
1: Rising edge of the counter input signal (TCLK)
Counter Clock Select (Default: 0)
This bit specifies the timer clock.
0: Internal clock (IMBUSCLK)
1: External input clock (TCLK)
Timer Mode (Default: 00)
This bit specifies the timer operation mode.
11: Reserved
10: Watchdog Timer mode (Timer 2), Reserved (Timer 0, 1)
01: Pulse Generator mode (Timer 0, 1), Reserved (Timer 2)
00: Interval Timer mode
Figure 12.4.1 Timer Control Register
Reserved
8
12-10
TCE
R/W
7
0
CCDE
R/W
6
0
Description
CRE
R/W
TMTCR0
TMTCR1
TMTCR2
5
0
Chapter 12 Timer/Counter
Reserved
4
ECES
R/W
3
0
0xF000
0xF100
0xF200
CCS
R/W
2
0
1
TMODE
R/W
00
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
16
0
⎯
⎯
: Type
: Initial value
: Type
: Initial value