P80C557E4EFB NXP Semiconductors, P80C557E4EFB Datasheet - Page 18

• Manufacturer Part Number: P80C557E4EFB
• Manufacturer: NXP Semiconductors

Specifications of P80C557E4EFB

• Cpu Family: 80C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 16MHz
• Interface Type: I2C/UART
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Total Internal Ram Size: 1KB
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
Table 10. Description of ADCON bits
1999 Mar 02
SYMBOL
ADCON.7
ADCON.6
ADCON.5
ADCON.4
ADCON.3
ADCON.2
ADCON.1
ADCON.0
Single-chip 8-bit microcontroller
ADPR1
ADPR0
ADPOS
ADINT
ADSST
ADCSA
ADSRE
ADSFE
BIT
AV
AV
AV
AV
ADEXS
ADC0
ADC7
ref+
SS1
ref–
DD1
FUNCTION
Control bit for the prescaler.
Control bit for the prescaler.
ADPR1=0 ADPR0=0 Prescaler divides by 2 (default by reset)
ADPR1=0 ADPR0=1 Prescaler divides by 4
ADPR1=1 ADPR0=0 Prescaler divides by 6
ADPR1=1 ADPR0=1 Prescaler divides by 8
ADPOS is reserved for future use. Must be ’0’ if ADCON is written.
ADC interrupt flag. This flag is set when all selected analog inputs are converted, as well in continuous
scan as in one-time scan mode. An interrupt is invoked if this interrupt is enabled. ADINT must be cleared
by software. It cannot be set by software.
ADC start and status. Setting this bit by software or by hardware (via ADEXS input) starts the A/D
conversion of the selected analog inputs. ADSST stays a ‘one’ in continuous scan mode. In one-time scan
mode, ADSST is cleared by hardware when the last selected analog input channel has been converted. As
long as ADSST is ’1’, new start commands to the ADC-block are ignored.
An A/D conversion in progress is aborted if ADSST is cleared by software.
1
0
1
0
1
0
ADPSS
=
=
=
=
=
=
Continuous scan of the selected analog inputs after a start of an A/D conversion.
One-time scan of the selected analog inputs after a start of an A/D conversion.
A rising edge at input ADEXS will start the A/D conversion and generate a capture signal.
A rising edge at input ADEXS has no effect.
A falling edge at input ADEXS will start the A/D conversion and generate a capture signal.
A falling edge at input ADEXS has no effect.
8
SCAN LOGIC
Figure 15. Functional diagram of AD converter.
ANALOG
ADCON
Mux.
8
INTERNAL BUS
18
P83C557E4/P80C557E4/P89C557E4
COMPARATOR
DAC
ADRSH
Read
+
–
10–bit result
2 LATCHES
registers
8x
2
2
10
ADRSL
Read
SAR
10
10
n
8
8
Product specification