P80C557E4EFB NXP Semiconductors, P80C557E4EFB Datasheet - Page 66

• Manufacturer Part Number: P80C557E4EFB
• Manufacturer: NXP Semiconductors

Specifications of P80C557E4EFB

• Cpu Family: 80C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 16MHz
• Interface Type: I2C/UART
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Total Internal Ram Size: 1KB
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
AC ELECTRICAL CHARACTERISTICS (Continued)
All values referred to V
NOTES:
1. A device must internally provide a hold time of at least 300 ns from the SDA signal (referred to the V
2. The maximum t
3. A fast-mode I
4. C
Table 46. External clock drive XTAL1 (refer to Figure 57)
NOTE:
1. t
1999 Mar 02
SYMBOL
I
f
t
t
t
t
t
t
t
t
t
t
C
t
SYMBOL
t
t
t
t
t
t
2
SCL
BUF
HD; STA
LOW
HIGH
SU; STA
HD; DAT
SU; DAT
FD
FD
SU
SP
CLK
CLKH
CLKL
CLKR
CLKF
CYC
Single-chip 8-bit microcontroller
C Interface timing (refer to Figure 63)
b
bridge the undefined region of the falling edge of SCL.
will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period
of the SCL signal, it must output the next data bit to the SDA line t
I
, t
, t
;
2
CYC
STO
C-bus specification) before the SCL line is released.
b
FC
FC
1)
= total capacitance of one bus line in pF.
= 12 f
CLK
XTAL1 Period
XTAL1 HIGH time
XTAL1 LOW time
XTAL1 rise time
XTAL1 fall time
Controller cycle time
SCL clock frequency
Bus free time between a STOP and START condition
Hold time (repeated) START condition. After this period, the
first clock pulse is generated
LOW period of the SCL clock
High period of the SCL clock
Set-up time for a repeated START condition
Data hold time:
for CBUS competible masters (see Section 9, Notes 1, 3)
for I
Data set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Set-up time for STOP condition
Capacitive load for each bus line
Pulse width of spikes which must be suppressed by the input
filter
2
C-bus device can be used in a standard-mode I
HD,DAT
2
C-bus devices
IH
and V
has only to be met if the device does not stretch the LOW period (t
IL max
levels.
PARAMETER
PARAMETER
2
C-bus system, but the requirement t
Rmax
66
P83C557E4/P80C557E4/P89C557E4
+ t
SU,DAT
= 1000 + 250 = 1250 ns (according to the standard-mode
Standard-mode
MIN
250
4.7
4.0
4.7
4.0
4.7
5.0
4.0
0
0
–
–
–
–
1
I
2
C-bus
LOW
0.75
MIN
63
20
20
f
VARIABLE CLOCK
–
–
CLK
MAX
1000
) of the SCL signal.
100
300
400
–
–
–
–
–
–
–
–
= 3.5 to 16 MHz
SU,DAT
IH min
0.1C
0.1C
of the SCL signal) in order to
100
> 250 ns must then be met. This
20 +
20 +
MIN
1.3
0.6
1.3
0.6
0.6
0.6
0
0
–
–
0
1
Fast-mode
MAX
3
b
b
286
3.4
20
20
I
4
4
2
–
–
C-bus
MAX
0.9
400
300
300
400
Product specification
50
–
–
–
–
–
–
–
–
2
UNIT
ns
ns
ns
ns
ns
s
UNIT
kHz
ns
ns
ns
pF
ns
s
s
s
s
s
s
s