P80C557E4EFB NXP Semiconductors, P80C557E4EFB Datasheet - Page 26

• Manufacturer Part Number: P80C557E4EFB
• Manufacturer: NXP Semiconductors

Specifications of P80C557E4EFB

• Cpu Family: 80C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 16MHz
• Interface Type: I2C/UART
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Total Internal Ram Size: 1KB
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
Table 18. Description of CTCON bits
The contents of the Compare Registers CM0, CM1 and CM2 are
continuously compared with the counter value of Timer T2. When a
match occurs, an interrupt may be invoked. A match of CM0 sets
the bits 0–5 of Port 4, a CM1 match resets these bits and a CM2
match toggles bits 6 and 7 of Port 4, provided these functions are
enabled by the STE respectively RTE registers. A match of CM0
and CM1 at the same time results in resetting bits 0–5 of Port 4.
CM0, CM1 and CM2 are reset by the RSTIN signal.
Table 19. Description of TM2IR bits
1999 Mar 02
Single-chip 8-bit microcontroller
SYMBOL
SYMBOL
CTN3
CTP3
CTN2
CTP2
CTN1
CTP1
CTN0
CTP0
T2OV
CMI2
CMI1
CMI0
CTI3
CTI2
CTI1
CTI0
TM2IR (C8H)
CTCON (EBH)
CTCON.7
CTCON.6
CTCON.5
CTCON.4
CTCON.3
CTCON.2
CTCON.1
CTCON.0
TM2IR.7
TM2IR.6
TM2IR.5
TM2IR.4
TM2IR.3
TM2IR.2
TM2IR.1
TM2IR.0
BIT
BIT
T2OV
CTN3
Capture Register 3 triggered by a falling edge on CT3I
Capture Register 3 triggered by a rising edge on CT3I
Capture Register 2 triggered by a falling edge on CT2I
Capture Register 2 triggered by a rising edge on CT2I
Capture Register 1 triggered by a falling edge on CT1I
Capture Register 1 triggered by a rising edge on CT1I
Capture Register 0 triggered by a falling edge on CT0I
Capture Register 0 triggered by a rising edge on CT0I
FUNCTION
Timer T2 16-bit overflow interrupt flag
CM2 interrupt flag
CM1 interrupt flag
CM0 interrupt flag
CT3 interrupt flag
CT2 interrupt flag
CT1 interrupt flag
CT0 interrupt flag
7
7
CMI2
CTP3
Figure 23. Capture control register (CTCON).
6
6
Figure 24. Interrupt flag register (TM2IR).
CMI1
CTN2
5
5
26
CMI0
CTP2
4
P83C557E4/P80C557E4/P89C557E4
4
FUNCTION
CTI3
CTN1
3
3
CTI2
CTP1
2
2
CTI1
CTN0
1
1
Product specification
CTI0
CTP0
0
0