P80C557E4EFB NXP Semiconductors, P80C557E4EFB Datasheet - Page 24

• Manufacturer Part Number: P80C557E4EFB
• Manufacturer: NXP Semiconductors

Specifications of P80C557E4EFB

• Cpu Family: 80C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 16MHz
• Interface Type: I2C/UART
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Total Internal Ram Size: 1KB
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
6.7.2 Timer T2
Timer T2 is a 16 bit timer/counter which has capture and compare
facilities. The operational diagram is shown in Figure 21.
The 16 bit timer/counter is clocked via a prescaler with a
programmable division factor of 1, 2, 4 or 8. The input of the
prescaler is clocked with 1/12 of the clock frequency, or by an
external source connected to the T2 input, or it is switched off. The
maximum repetition rate of the external clock source is f
twice that of Timer 0 and Timer 1. The prescaler is incremented on a
rising edge. It is cleared if its division factor or its input source is
changed, or if the timer/counter is reset (see also Figure 22:
TM2CON). T2 is readable ’on the fly’, without any extra read
latches; this means that software precautions have to be taken
against misinterpretation at overflow from least to most significant
1999 Mar 02
Single-chip 8-bit microcontroller
f
T2ER
CLK
RT2
off
T2
STE
TG
TG
S
S
S
S
S
S
External reset
enable
1/12
RTE
R
R
R
R
R
R
T
T
CT0I
CT0
CTI0
INT
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
Prescaler
I/O port 4
Figure 21. Block diagram of Timer 2.
CT1I
CLK
/12,
CT1
CTI1
INT
T2 Counter
S = set
R = reset
T
TG = toggle status
= toggle
24
P83C557E4/P80C557E4/P89C557E4
byte while T2 is being read. T2 is not loadable and is reset by the
RST signal or at the positive edge of the input signal RT2, if
enabled. In the Idle or Power-down Mode the timer/counter and
prescaler are reset and halted.
T2 is connected to four 16-bit Capture Registers: CT0, CT1, CT2
and CT3. A rising or falling edge on the inputs CT0I, CT1I, CT2I or
CT3I (alternative function of Port 1) results in loading the contents of
T2 into the respective Capture Registers and an interrupt request.
Using the Capture Register CTCON (see Figure 23), these inputs
may invoke capture and interrupt request on a positive, a negative
edge or on both edges. If neither a positive nor a negative edge is
selected for capture input, no capture or interrupt request can be
generated by this input.
CMO (S)
COMP
CT2I
8-bit overflow interrupt
16-bit overflow interrupt
CT2
INT
T2 SFR address: TML2 = lower 8 bits
CTI2
INT
CM1 (R)
COMP
TMH2 = higher 8 bits
INT
CT3I
CT3
CM2 (T)
COMP
CTI3
INT
Product specification
INT