P80C557E4EFB NXP Semiconductors, P80C557E4EFB Datasheet - Page 65

• Manufacturer Part Number: P80C557E4EFB
• Manufacturer: NXP Semiconductors

Specifications of P80C557E4EFB

• Cpu Family: 80C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 16MHz
• Interface Type: I2C/UART
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Total Internal Ram Size: 1KB
• # I/os (max): 40
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
11. AC CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS
V
V
T
T
C1 = 100 pF for Port 0, ALE and PSEN ; C1 = 80 pF for all other outputs unless otherwise specified.
1999 Mar 02
amb
amb
1/t
t
t
t
t
t
t
t
t
t
t
t
Data Memory
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
UART Timing – Shift Register Mode (Test Conditions: T
t
t
t
t
t
DD
DD
SYMBOL
LHLL
AVLL
LLAX
LLIV
LLPL
PLPH
PLIV
PXIX
PXIZ
AVIV
PLAZ
AVLL
LLAX
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
AVDV
LLWL
AVWL
QVWX
QVWH
WHQX
RLAZ
WHLH
XLXL
QVXH
XHQX
XHDX
XHDV
Single-chip 8-bit microcontroller
CLK
= 5 V
= 5 V
= 0 C to +70 C, t
= –40 C to +85 C, t
10% (EBx), V
10% (EFx), V
FIGURE
61, 62
61, 62
61, 62
61, 62
61, 62
60
60
60
60
60
60
60
60
60
60
60
60
61
62
61
61
61
61
61
62
62
62
61
64
64
64
64
64
CLK
SS
SS
CLK
System clock frequency
ALE pulse width
Address valid to ALE LOW
Address hold after ALE LOW
ALE LOW to valid instruction in
ALE LOW to PSEN LOW
PSEN pulse width
PSEN LOW to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN LOW to address float
Address valid to ALE LOW
Address hold after ALE LOW
RD pulse width
WR pulse width
RD LOW to valid data in
Data hold after RD
Data float after RD
ALE LOW to valid data in
Address to valid data in
ALE LOW to RD or WR LOW
Address valid to WR LOW or RD LOW
Data valid to WR transition
Data before WR
Data hold after WR
RD low to address float
RD or WR HIGH to ALE HIGH
Serial port clock cycle time
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
min = 63 ns for P8xC557E4EBx
= 0 V, t
= 0 V, t
min = 63 ns for P8xC557E4EFx
CLK
CLK
PARAMETER
min = 1/fmax (maximum operating frequency)
min = 1/fmax (maximum operating frequency)
amb
= 0 C to +70 C; V
12MHz CLOCK
MIN
127
205
400
400
200
203
433
700
1.0
43
53
53
43
48
33
33
43
50
0
0
0
65
P83C557E4/P80C557E4/P89C557E4
MAX
234
145
312
252
517
585
300
123
700
59
10
97
0
SS
= 0 V; Load Capacitance = 80pF)
16MHz CLOCK
0.75
MIN
143
275
275
138
120
288
492
85
23
33
33
23
28
13
13
23
0
0
8
0
MAX
150
208
148
350
398
238
103
492
83
38
10
55
0
10t
6t
6t
4t
7t
2t
2t
3t
3t
t
t
t
t
t
t
t
t
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
12t
CLK
CLK
CLK
CLK
CLK
VARIABLE CLOCK
MIN
3.5
0
0
0
CLK
–40
–30
–30
–40
–35
–100
–100
–130
–50
–150
–50
–40
–117
–40
–45
–50
–133
10t
4t
3t
5t
5t
8t
9t
2t
3t
t
t
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
Product specification
MAX
16
10
0
–100
–105
–25
–105
–165
–150
–165
+40
–70
+50
–133
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s