TXC-04251AIPQ Transwitch Corporation, TXC-04251AIPQ Datasheet - Page 48

• Manufacturer Part Number: TXC-04251AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-04251AIPQ

• Pin Count: 160
• Screening Level: Industrial
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

TXC-04251-MB
Ed. 4, March 2000
QT1M
TXC-04251
RESETS
The Quad T1 Mapper has several reset options. These include a full hardware and software device reset, par-
tial software resets, and counter software resets. All of the software reset bits are self-clearing and do not
require a 0 to be written to a register location after the reset is applied by setting the bit to 1. Upon power-up,
when the RESET bit (bit 7 in 15 hex) is written with a 1, or an active low is placed on the RESET pin (pin 155),
the add bus data and the port T1 interfaces are forced to a high impedance state until the device is initialized or
reinitialized. The AAHZE, BAHZE, and RnEN control bits must be written with zeros in order to enable the bus
and line interfaces. In addition, the AAIND, BAIND, AADD and BADD pins are forced off. All performance
counters are reset, and the alarms (except AnLOP , BnLOP) are reset. The control bits are also forced to zero,
and the various FIFOs are recentered. A hardware reset can only be applied after the clocks are stable, and
must be present for a minimum of 150 nanoseconds.
Writing 1 to a RnSETS software reset control bit for any of the ports resets the performance counters, re-cen-
ters the FIFO, and clears the alarms, except the AnLOP, BnLOP alarms, which will set for port n. The loss of
pointer alarms will recover when a valid pointer is received. The control bits will not be reset.
Writing 1 to a RnSETC counter reset control bit for any of the ports resets the performance counters for that
port. This feature allows the performance measurements to start at the same time for a port.
Writing 1 to control bits RESTAB or RESTBB resets the alarms for each of the two buses, A side and B side.
DATA THROUGHPUT DELAY
On the Receive side (SONET/SDH to T1) the mapper delay in T1 bit times will run from a nominal delay of 85
to 90 clocks, up to a maximum of 200 clocks with the Leak and Desynchronizer FIFOs near the saturation
point. When using Bypass or AMI, there will be an eleven or ten clock nominal reduction in those figures, as the
calculations were payload with the assumption of B8ZS encoding, which gives the maximum delay.
On the Transmit side (T1 to SONET/SDH) the maximum delay is approximately 85 clocks with a nominal delay
of around 40 to 45 T1 bit times. The delay is less for AMI or NRZ than for B8ZS decoding.
DATA SHEET
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