TXC-04251AIPQ Transwitch Corporation, TXC-04251AIPQ Datasheet - Page 6

• Manufacturer Part Number: TXC-04251AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-04251AIPQ

• Pin Count: 160
• Screening Level: Industrial
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

TXC-04251-MB
Ed. 4, March 2000
QT1M
TXC-04251
bus timing, and from software instructions specifying which VT/TU number is being dropped/added. When the
device is configured for add bus timing, the add bus, parity, and add indicator signals are derived from the add
clock, C1J1V1 and SPE signals.
The A Receive block is identical to the B Receive block. The VT/TU Terminate block is repeated 8 times, two for
each port (A and B sides). The Destuff, Desync, and AMI/B8ZS Coder Blocks are repeated four times, one for
each port. The interface between a drop bus and Receive block consists of 12 input leads (pins), and an
optional output lead: a byte clock, byte-wide data, a C1J1 indicator which may be carrying a V1 indication mak-
ing the signal a C1J1V1 indicator, an SPE indicator, and an odd parity bit for the last-named three signals. Par-
ity is selectable by control bits for even parity and for the data byte only. The output lead is an optional VT/TU
select indicator signal. The Drop C1J1V1 signal is used in conjunction with the Drop SPE signal to determine
the location of the various pulses. The C1 pulse identifies the location of the C1 byte when the SPE signal is
low. A single J1 pulse identifies the starting location of the J1 byte in the VC-4 format, when the SPE signal is
high. Three J1 pulses are provided for the STS-3 format, each identifying the starting location of the J1 byte in
each of the STS-1 signals.
The Quad T1 Mapper can operate with a V1 pulse in the C1J1V1 signal, or it can use an internal H4 detector
for determining the location of the V1 pulse. The V1 pulse location is used to determine the location of the
pointer byte V1. For STM-1 VC-4 operation, if the C1J1V1 signal is used, a single V1 pulse must occur three
drop bus clock cycles every four frames following the J1 pulse. For STS-3 operation, three V1 pulses must be
present every four frames. Each of the three V1 pulses must be present three clock cycles after the corre-
sponding J1 pulse, when the SPE signal is high. For example, in a VC-4 signal, the J1 pulse identifies the J1
byte location (defined as the starting location for the VC-4) in the POH bytes. In the next column (first clock
cycle) all the rows are assigned as fixed stuff. Similarly, in the next column (second clock cycle) all the rows are
assigned as fixed stuff. The next column (third clock cycle) defines the start of TUG-3 A. This column is where
the V1 pulse occurs every four frames. However, the actual V1 byte location is six clock cycles after the V1
pulse.
For STS-1 operation, one V1 must be present if the C1J1V1 signal is used. The V1 pulse must occur on the
next clock cycle after J1, and when the SPE signal is high. The J1 pulse identifies the J1 byte location (defined
as the starting location for the STS-1) in the POH bytes. In the next column (first clock cycle) the VTs start.
Thus, the V1 pulse identifies the starting location of the first V1 byte in the signal. The rest of the V1 bytes for
the 21 VT1.5/TU-11s are aligned regarding their starting point with respect to the V1 pulse.
Each bus is monitored for parity errors, loss of clock, H4 multiframe alignment if selected, and an upstream
SONET/SDH AIS indication. The Quad T1 Mapper can monitor either the TOH E1 bytes or the H1/H2 bytes for
an AIS indication. Which E1 byte and H1/H2 bytes are selected is a function of the VT/TU selected.
Each VT/TU Terminate block (A and B side) performs pointer processing based on the location of the V1 and
V2 bytes. The pointer bytes are monitored for loss of pointer, VT AIS indication, and NDF. The pointer tracking
process is based on the latest ETSI standard, which also meets ANSI/Bellcore requirements. Pointer incre-
ments and decrements are also counted, and the SS-bits are monitored for the correct value. This block also
monitors the various alarms found in the V5 and Z7 bytes, including signal label mismatch detection,
unequipped status detection, BIP-2 parity error detection and error counter, FEBE counter, and the RDI indica-
tions.
A control bit for each port selects the VT/TU from either the A Drop or B Drop bus. The VT/TU is destuffed in
the Destuff block using majority logic rules for the three sets of three justification control bits to determine if the
two S-bits are data bits or frequency justification bits.
The Desync block removes the effects on the T1 output of systemic jitter that might occur because of signal
mappings and pointer movements in the network. The Desync block contains two parts, a pointer leak buffer,
and a T1 loop buffer. The pointer leak buffer can accept up to five consecutive pointer movements, and can
adjust the effect over time. The T1 Loop Buffer consists of a digital loop filter, which is designed to track the fre-
quency of the received T1 signal and to remove both transmission and stuffing jitter.
DATA SHEET
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