TXC-04251AIPQ Transwitch Corporation, TXC-04251AIPQ Datasheet - Page 66

• Manufacturer Part Number: TXC-04251AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-04251AIPQ

• Pin Count: 160
• Screening Level: Industrial
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

TXC-04251-MB
Ed. 4, March 2000
QT1M
TXC-04251
Address
(cont.)
11
Bit
6
5
4
3
2
1
0
Symbol
DRPBT
LATEN
RAISE
RCLKI
TCLKI
TAISE
ABD
Drop Bus Timing: Enabled when a 1 is written to control bit SBTEN. A 1
selects the drop bus timing mode, while a 0 selects the add bus timing mode.
See table above.
Add Bus Delay: A 0 delays the add bus data with respect to the drop bus by
one clock cycle. A 1 delays the add bus data with respect to the drop bus by
one additional clock cycle, for a total of two clock cycles. This bit operates in
both the drop bus and add bus timing modes.
Latch On Alarm Transitions Enable Bit: A 1 enables the IPOS and INEG
control bits at Address 12H, Bits 5 and 4. A 0 disables the states of the IPOS
and INEG control bits, and causes the event alarm bits (latched alarm bits in
the registers) to latch on the positive level of an alarm.
Transmit T1 Line AIS Enable: A common control for all four ports. A 1
enables a T1 AIS (unframed all ones) to be generated and sent when a T1
line input loss of signal, or loss of clock, occurs for port n.
Transmit T1 Line Clock Inversion: A common control for the four ports. A 0
enables transmit data to be clocked in on the negative clock edges. A 1
enables data to be clocked in on the positive clock edges.
Receive T1 Line AIS Enable: A common control for the four ports. A 1
enables a receive T1 AIS to be sent when internal defined alarms occur for
port n. A T1 AIS is an unframed all ones signal. For example, receive AIS for
port 1 will be generated:
- When R1SEL is 0 and RAISE is 1 (drop VT from A side)
- When R1SEL is 1 and RAISE is 1 (drop VT from B side)
- Receive FIFO Error (R1FFE) and RAISE is 1
- A 1 written to send receive AIS (R1AIS)
The AIS will be sent for one multiframe when a receive FIFO error occurs.
The n in AnUAISI, BnUAISI, AnDH4E and BnDH4E represents the STS-1 or
TUG in which the VT/TU has been selected.
Receive T1 Line Clock Inversion: A common control for the four ports. A 0
enables the T1 receive data signal to be clocked out on positive clock edges.
A 1 causes T1 data to be clocked out on negative clock edges.
- Loss of pointer detected (A1LOP)
- VT AIS detected (A1AIS)
- A Drop Bus Loss Of Clock (ADLOC)
- A Drop Bus Upstream AIS detected (AnUAISI) when HEAISE is 1.
- A Drop H4 Error (AnDH4E) when DV1SEL is 0
- Unequipped signal label (A1UNEQ) and UQAE is 1
- Mismatch signal label (A1SLER)
- Loss of pointer detected (B1LOP)
- VT AIS detected (B1AIS)
- B Drop Bus Loss Of Clock (BDLOC)
- B Drop Bus Upstream AIS detected (BnUAISI) and HEAISE is 1
- B Drop H4 Error (BnDH4E) when DV1SEL is 0
- Unequipped signal label (B1UNEQ) and UQAE is 1
- Mismatch signal label (B1SLER)
DATA SHEET
- 66 -
Description