TXC-04251AIPQ Transwitch Corporation, TXC-04251AIPQ Datasheet - Page 71

• Manufacturer Part Number: TXC-04251AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-04251AIPQ

• Pin Count: 160
• Screening Level: Industrial
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

COMMON REGISTERS - OPERATIONS DESCRIPTIONS
Address
17
18
19
7, 5,
6, 4,
7, 5,
6, 4,
7, 6,
3, 2,
3, 1
2, 0
3, 1
2, 0
5, 4
1, 0
Bit
TFIFOnA
TFIFOnB
TPORTn
Symbol
RFIFOn
RPTnA
(n=4-1)
RPTnB
(n=4-1)
(n=4-1)
(n=4-1)
(n=4-1)
(n=4-1)
Receive A Side Status Interrupt Mask Bit: A 1 enables a hardware
interrupt and software interrupt indication (INT) when an alarm has occurred
in an A-side alarm register (mask bits for registers 30, 60, 90, and C0) when
PnMSK is set for port n. A 0 disables the A side receive alarms for port n from
causing an interrupt.
Receive B Side Status Interrupt Mask Bit: A 1 enables a hardware
interrupt and software interrupt indication (INT) when an alarm has occurred
in a B-side alarm register (mask bits for registers 3A, 6A, 9A, and CA) when
PnMSK is set for port n. A 0 disables the B side receive alarms for port n from
causing an interrupt.
Transmit FIFO Error A Side Status Interrupt Mask Bit: A 1 enables a
hardware interrupt and software interrupt indication (INT) when an alarm has
occurred for an A-side transmit FIFO (mask bits for bit 4 in registers 44, 74,
A4, and D4) when PnMSK is set for port n. A 0 disables a transmit FIFO error
A side alarm for port n from causing an interrupt.
Transmit FIFO Error B Side Status Interrupt Mask Bit: A 1 enables a
hardware interrupt and software interrupt indication (INT) when an alarm has
occurred for a B-side transmit FIFO (mask bits for bit 3 in registers 44, 74, A4,
and D4) when PnMSK is set for port n. A 0 disables a transmit FIFO error B
side alarm for port n from causing an interrupt.
Transmit Status Interrupt Mask Bit: A 1 enables a hardware interrupt and
software interrupt indication (INT) when an alarm has occurred for one of the
transmit alarms (mask bits for TnLOS (bit 2), TnLOC (bit 1) and TnDAIS (bit
0) in registers 44, 74, A4, and D4) when PnMSK is set for port n. A 0 disables
a transmit alarm from causing an interrupt.
Receive FIFO Error Status Interrupt Mask Bit: A 1 enables a hardware
interrupt and software interrupt indication (INT) when an alarm has occurred
for a receive FIFO (mask bits for bit 7 in registers 44, 74, A4, and D4) when
PnMSK is set for port n. A 0 disables a receive FIFO error alarm for port n
from causing an interrupt.
DATA SHEET
- 71 -
Description
Ed. 4, March 2000
TXC-04251
TXC-04251-MB
QT1M