TXC-04251AIPQ Transwitch Corporation, TXC-04251AIPQ Datasheet - Page 74

• Manufacturer Part Number: TXC-04251AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-04251AIPQ

• Pin Count: 160
• Screening Level: Industrial
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

TXC-04251-MB
Ed. 4, March 2000
QT1M
TXC-04251
Address
(cont.)
25
26
27
7-0
4-3
Bit
1
0
7
6
5
2
1
0
A2DH4E A Drop Bus Loss of H4 Indication - AU-3 B/STS-1 No. 2: Loss of multiframe
A1DH4E A Drop Bus Loss of H4 Indication - AU-3 A/STS-1 No. 1, AU-4 VC-4, or STS-
B3UAISI B side Received Upstream AIS Indication - AU-3 C/STS-1 No. 3: When
B2UAISI B side Received Upstream AIS Indication - AU-3 B/STS-1 No. 2: When
B1UAISI B side Received Upstream AIS Indication - AU-3 A/STS-1 No. 1, AU-4 VC-4,
Symbol
BDLOC
BALOC
BDPAR
Unused
for AUG-3 B/STS-1 no. 2 is declared if one or more H4 values differ from those of
a two-bit counter once per multiframe for two consecutive multiframes, when
control bit DV1SEL is 0. The received H4 multiframe sequence is 00, 01, 10, and
11. The multiframe detector will continue to operate in a free running mode, but
will lock to a new H4 sequence after one multiframe sequence has been
received correctly. This H4 detector is disabled when the format is an AU-4 VC-
4, or STS-1. This bit is forced to 1 at power-up.
1: Loss of multiframe for AUG-3 A/STS-1 No. 1 or AU-4 VC-4 is declared if one or
more H4 values differ from those of a two-bit counter once per multiframe for two
consecutive multiframes, when control bit DV1SEL is 0. The received H4
multiframe sequence is 00, 01, 10, and 11. The multiframe detector will continue
to operate in a free running mode, but will lock to a new H4 sequence after one
multiframe sequence has been received correctly. This bit is forced to 1 at
power-up.
Same bit definitions as in register 27 hex, except the bits are latched.
B Drop Bus Loss Of Clock: A 1 indicates that the B Drop bus has detected a
loss of clock. An alarm occurs when the input drop clock is stuck high or low for
the equivalent of 1000 ns +/- 500 ns. Recovery occurs on the first clock
transition.
B Add Bus Loss Of Clock: A 1 indicates that the B Add bus has detected a loss
of clock, when add bus timing is selected. A loss of clock alarm forces the add
data and parity bit to a high impedance state, and the add indicator off for the
duration of the alarm. An alarm occurs when the input drop clock is stuck high or
low for 10 or more clock cycles. Recovery occurs on the first clock transition.
B Drop Bus Parity Error Detected: A 1 indicates that an even or odd parity
error has been detected in the B Drop bus signals. Other than an alarm
indication, no action is taken. Parity is monitored for each drop bus clock cycle.
Unused: These bits read out as 0.
control bit SE1AIS is 0, a 1 indicates that AIS has been detected in the H1/H2
bytes for AU-3 C/STS-1 No. 3. When control bit SE1AIS is 1, a 1 indicates that
AIS has been detected in the E13 byte for AU-3 C/STS-1 No. 3. Disabled when
the format is a AU-4 VC-4, or STS-1.
control bit SE1AIS is 0, a 1 indicates that AIS has been detected in the H1/H2
bytes for AU-3 B/STS-1 No. 2. When control bit SE1AIS is 1, a 1 indicates that
AIS has been detected in the E12 byte for AU-3 B/STS-1 No. 2. Disabled when
the format is a AU-4 VC-4, or STS-1
or STS-1: When control bit SE1AIS is 0, a 1 indicates that AIS has been
detected in the H1/H2 bytes for AU-3 A/STS-1 No. 1, or in the AU-4 VC-4 signal.
When control bit SE1AIS is 1, a 1 indicates that AIS has been detected in the
E11 byte for AU-3 A/STS-1 No. 1, AU-4 VC-4, or STS-1 signal.
DATA SHEET
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Description