ADSP-BF561SKBCZ600 Analog Devices Inc, ADSP-BF561SKBCZ600 Datasheet - Page 11

• Manufacturer Part Number: ADSP-BF561SKBCZ600
• Description: DSP Fixed-Point 16-Bit 600MHz 600MIPS 256-Pin CSP-BGA
• Manufacturer: Analog Devices Inc

Specifications of ADSP-BF561SKBCZ600

• Package: 256CSP-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 600 MHz
• Ram Size: 32 KB
• Device Million Instructions Per Second: 600 MIPS

Preliminary Technical Data
Entire Field Mode
In this mode, the entire incoming bitstream is read in through
the PPI. This includes active video, control preamble sequences,
and ancillary data that may be embedded in horizontal and ver-
tical blanking intervals.
Though not explicitly supported, ITU,-656 output functionality
can be achieved by setting up the entire frame structure (includ-
ing active video, blanking and control information) in memory
and streaming the data out of the PPI in a frame sync-less mode.
The processor’s 2D DMA features facilitate this transfer by
allowing the static frame buffer (blanking and control codes) to
be placed in memory once, and simply updating the active video
information on per-frame basis.
These modes support ADC/DAC connections, as well as video
communication with hardware signaling. Many of the modes
support more than one level of frame synchronization. If
desired, a programmable delay can be inserted between asser-
tion of a frame sync and reception/transmission of data.
DYNAMIC POWER MANAGEMENT
The ADSP-BF561 provides four operating modes, each with a
different performance/power profile. In addition, Dynamic
Power Management provides the control functions to dynami-
cally alter the processor core supply voltage, further reducing
power dissipation. Control of clocking to each of the ADSP-
BF561 peripherals also reduces power consumption. See
for a summary of the power settings for each mode.
Full-On Operating Mode – Maximum Performance
In the Full-On mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the default execution state in which maximum performance
can be achieved. The processor cores and all enabled peripherals
run at full speed.
Active Operating Mode – Moderate Power Savings
In the Active mode, the PLL is enabled but bypassed. Because
the PLL is bypassed, the processor’s core clock (CCLK) and sys-
tem clock (SCLK) run at the input clock (CLKIN) frequency. In
this mode, the CLKIN to CCLK multiplier ratio can be changed,
although the changes are not realized until the Full-On mode is
entered. DMA access is available to appropriately configured L1
memories.
In the Active mode, it is possible to disable the PLL through the
PLL Control register (PLL_CTL). If disabled, the PLL must be
re-enabled before transitioning to the Full-On or Sleep modes.
Table 3. Power Settings
Mode
Full On
Active
PLL
Enabled No
Enabled/
Disabled
PLL
Bypassed
Yes
Core
Clock
(CCLK)
Enabled Enabled On
Enabled Enabled On
System
Clock
(SCLK)
Rev. PrC | Page 11 of 52 | April 2004
Table 3
Core
Power
Table 3. Power Settings (Continued)
Hibernate Operating Mode—Maximum Static Power
Savings
The Hibernate mode maximizes static power savings by dis-
abling the voltage and clocks to the processor core (CCLK) and
to all the synchronous peripherals (SCLK). The internal voltage
regulator for the processor can be shut off by writing b#00 to the
FREQ bits of the VR_CTL register. This disables both CCLK
and SCLK. Furthermore, it sets the internal power supply volt-
age (V
dissipation. Any critical information stored internally (memory
contents, register contents, etc.) must be written to a non-vola-
tile storage device prior to removing power if the processor state
is to be preserved. Since V
of the external pins tri-state, unless otherwise specified. This
allows other devices that may be connected to the processor to
have power still applied without drawing unwanted current.
The internal supply regulator can be woken up by asserting the
RESET pin.
Sleep Operating Mode—High Dynamic Power Savings
The Sleep mode reduces power dissipation by disabling the
clock to the processor core (CCLK). The PLL and system clock
(SCLK), however, continue to operate in this mode. Typically an
external event will wake up the processor. When in the Sleep
mode, assertion of wakeup will cause the processor to sense the
value of the BYPASS bit in the PLL Control register (PLL_CTL).
When in the Sleep mode, system DMA access to L1 memory is
not supported.
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
The Deep Sleep mode maximizes power savings by disabling the
clocks to the processor cores (CCLK) and to all synchronous
peripherals (SCLK). Asynchronous peripherals will not be able
to access internal resources or external memory. This powered-
down mode can only be exited by assertion of the reset interrupt
(RESET). If BYPASS is disabled, the processor will transition to
the Full On mode. If BYPASS is enabled, the processor will tran-
sition to the Active mode.
Power Savings
As shown in
power domains. The use of multiple power domains maximizes
flexibility, while maintaining compliance with industry stan-
dards and conventions. By isolating the internal logic of the
ADSP-BF561 into its own power domain, separate from the I/O,
Mode
Sleep
Deep Sleep Disabled –
Hibernate
DDINT
) to 0 V to provide the lowest static power
Table
PLL
Enabled –
Disabled –
4, the ADSP-BF561 supports two different
PLL
Bypassed
DDEXT
is still supplied in this mode, all
Core
Clock
(CCLK)
Disabled Enabled On
Disabled Disabled On
Disabled Disabled Off
ADSP-BF561
System
Clock
(SCLK)
Core
Power