ADSP-BF561SKBCZ600 Analog Devices Inc, ADSP-BF561SKBCZ600 Datasheet - Page 39

• Manufacturer Part Number: ADSP-BF561SKBCZ600
• Description: DSP Fixed-Point 16-Bit 600MHz 600MIPS 256-Pin CSP-BGA
• Manufacturer: Analog Devices Inc

Specifications of ADSP-BF561SKBCZ600

• Package: 256CSP-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 600 MHz
• Ram Size: 32 KB
• Device Million Instructions Per Second: 600 MIPS

Preliminary Technical Data
Timer Cycle Timing
Table 27
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input fre-
quency of f
Table 27. Timer Cycle Timing
1
2
The minimum pulsewidths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPICLK input pins in PWM output mode.
The minimum time for t
Parameter
Timing Characteristics
t
t
Switching Characteristic
t
WL
WH
HTO
CLKOUT
(PWM OUTPUT MODE)
EXTERNAL CLOCK MODES)
and
(WIDTH CAPTURE AND
SCLK
Figure 19
/2 MHz.
TMRx
TMRx
Timer Pulsewidth Input Low
Timer Pulsewidth Input High
Timer Pulsewidth Output
HTO
describe timer expired operations. The
is one cycle, and the maximum time for t
2
1
1
Rev. PrC | Page 39 of 52 | April 2004
Figure 19. Timer PWM_OUT Cycle Timing
t
WL
HTO
equals (2
32
–1) cycles.
t
WH
t
HTO
Min
1
1
1
Max
(2
32
–1)
ADSP-BF561
Unit
SCLK cycles
SCLK cycles
SCLK cycles