ADSP-BF561SKBCZ600 Analog Devices Inc, ADSP-BF561SKBCZ600 Datasheet - Page 43

• Manufacturer Part Number: ADSP-BF561SKBCZ600
• Description: DSP Fixed-Point 16-Bit 600MHz 600MIPS 256-Pin CSP-BGA
• Manufacturer: Analog Devices Inc

Specifications of ADSP-BF561SKBCZ600

• Package: 256CSP-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 600 MHz
• Ram Size: 32 KB
• Device Million Instructions Per Second: 600 MIPS

Preliminary Technical Data
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving. The output enable time t
the point when a reference signal reaches a high or low voltage
level to the point when the output starts driving as shown in the
Output Enable/Disable diagram
t
switches to when the output voltage reaches 2.0V (output high)
or 1.0V (output low). Time t
output starts driving to when the output reaches the 1.0V or
2.0V trip voltage. Time t
t
enabled, the measurement value is that of the first pin to start
driving.
Output Disable Time
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by V is dependent on the capacitive load, C
load current, I
following equation:
The output disable time t
t
t
switches to when the output voltage decays V from the mea-
sured output high or output low voltage. t
with test loads C
EXAMPLE SYSTEM HOLD TIME CALCULATION
To determine the data output hold time in a particular system,
first calculate t
age and the input threshold for the device requiring the hold
ENA_MEASURED
ENA_MEASURED
DIS_MEASURED
DIS_MEASURED
V to be the difference between the ADSP-BF561's output volt-
(MEASURED)
(MEASURED)
t
DIS
V
V
OH
OL
OUTPUT STOPS DRIVING
L
DECAY
and t
is the interval from when the reference signal
–t
. This decay time can be approximated by the
is the interval from when the reference signal
L
TRIP
Figure 24. Output Enable/Disable
and I
DECAY
REFERENCE
t
V
V
t
DIS-MEASURED
. If multiple pins (such as the data bus) are
using the equation given above. Choose
OL
DECAY
OH
SIGNAL
t
L
(MEASURED) + V
DECAY
VOLTAGE TO BE APPROXIMATELY 1.5V.
(MEASURED) - V
, and with V equal to 0.5 V.
ENA
DIS
as shown in
TEST CONDITIONS CAUSE THIS
TRIP
is calculated as
=
is the difference between
HIGH-IMPEDANCE STATE.
(
C
(Figure
is the interval from when the
t
L
ENA
∆
V
ENA
) I
Figure
⁄
OUTPUT STARTS DRIVING
24). The time
L
DECAY
is the interval from
24.The time
t
2.0V
1.0V
ENA-MEASURED
is calculated
t
TRIP
(MEASURED)
(MEASURED)
Rev. PrC | Page 43 of 52 | April 2004
L
V
V
OL
OH
and the
time. A typical V will be 0.4 V. CL is the total bus capacitance
(per data line), and IL is the total leakage or three-state current
(per data line). The hold time will be t
disable time (i.e., t
Figure 25. Typical Output Delay or Hold vs. Load Capacitance (at Max Case
NOMINAL
-5
5
4
3
2
1
0
DSDAT
30
for an SDRAM write cycle).
60
Temperature)
LOAD CAPACITANCE - pF
90
DECAY
120
ADSP-BF561
plus the minimum
150
180
210