ADSP-BF561SKBCZ600 Analog Devices Inc, ADSP-BF561SKBCZ600 Datasheet - Page 30

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ADSP-BF561SKBCZ600

Manufacturer Part Number
ADSP-BF561SKBCZ600
Description
DSP Fixed-Point 16-Bit 600MHz 600MIPS 256-Pin CSP-BGA
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADSP-BF561SKBCZ600

Package
256CSP-BGA
Numeric And Arithmetic Format
Fixed-Point
Maximum Speed
600 MHz
Ram Size
32 KB
Device Million Instructions Per Second
600 MIPS
ADSP-BF561
Table 22. Serial Ports—Internal Clock
1
Table 23. Serial Ports—Enable and Three-State
1
Table 24. External Late Frame Sync
1
2
Referenced to drive edge.
Referenced to drive edge.
MCE = 1, TFS enable and TFS valid follow t
If external RFS/TFS setup to RSCLK/TSCLK > t
Parameter
Switching Characteristics
t
t
t
t
t
Parameter
Switching Characteristics
t
t
t
t
Parameter
Switching Characteristics
t
t
DFS
HOFS
DDT
HDT
SCLKIW
DTENE
DDTTE
DTENI
DDTTI
DDTLFSE
DTENLFSE
I
I
I
I
TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)
TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)
Transmit Data Delay After TSCLK
Transmit Data Hold After TSCLK
TSCLK/RSCLK Width
Data Enable Delay from External TSCLK
Data Disable Delay from External TSCLK
Data Enable Delay from Internal TSCLK
Data Disable Delay from Internal TSCLK
Data Delay from Late External TFS or External RFS with MCE = 1, MFD
= 0
Data Enable from late FS or MCE = 1, MFD = 0
1,2
DDTENFS
SCLK
/2 then t
and t
DDTLFSE
DDTLSCK
Rev. PrC | Page 30 of 52 | April 2004
1
.
1
and t
1
1
DTENLSCK
1
1,2
apply, otherwise t
DDTLFSE
1
1
and t
Min
TBD
TBD
4.5
Min
TBD
TBD
Min
TBD
Preliminary Technical Data
DTENLFS
apply.
Max
TBD
TBD
Max
TBD
TBD
Max
TBD
Unit
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
Unit
ns
ns

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