ADSP-BF561SKBCZ600 Analog Devices Inc, ADSP-BF561SKBCZ600 Datasheet - Page 12

• Manufacturer Part Number: ADSP-BF561SKBCZ600
• Description: DSP Fixed-Point 16-Bit 600MHz 600MIPS 256-Pin CSP-BGA
• Manufacturer: Analog Devices Inc

Specifications of ADSP-BF561SKBCZ600

• Package: 256CSP-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 600 MHz
• Ram Size: 32 KB
• Device Million Instructions Per Second: 600 MIPS

ADSP-BF561
the processor can take advantage of Dynamic Power Manage-
ment, without affecting the I/O devices. There are no
sequencing requirements for the various power domains.
Table 4. ADSP-BF561 Power Domains
The power dissipated by a processor is largely a function of the
clock frequency of the processor and the square of the operating
voltage. For example, reducing the clock frequency by 25%
results in a 25% reduction in dynamic power dissipation, while
reducing the voltage by 25% reduces dynamic power dissipation
by more than 40%. Further, these power savings are additive, in
that if the clock frequency and supply voltage are both reduced,
the power savings can be dramatic.
The Dynamic Power Management feature of the ADSP-BF561
allows both the processor’s input voltage (V
frequency (f
The savings in power dissipation can be modeled using the
Power Savings Factor and % Power Savings calculations.
Power Domain
All internal logic
I/O
CCLK
) to be dynamically controlled.
DDINT
VDD Range
V
V
DDINT
DDEXT
) and clock
Rev. PrC | Page 12 of 52 | April 2004
The Power Savings Factor is calculated as:
where the variables in the equations are:
The percent power savings is calculated as:
VOLTAGE REGULATION
The ADSP-BF561 processor provides an on-chip voltage regula-
tor that can generate processor core voltage levels 0.85V(-5% /
+10%) to 1.2V(-5% / +10%) from an external 2.25 V to 3.6 V
supply.
required to complete the power management system. The regu-
lator controls the internal logic voltage levels and is
programmable with the Voltage Regulator Control Register
(VR_CTL) in increments of 50 mV. To reduce standby power
consumption, the internal voltage regulator can be programmed
to remove power to the processor core while keeping I/O power
(V
applied, eliminating the need for external buffers. The voltage
regulator can be activated from this powerdown state by assert-
ing RESET, which will then initiate a boot sequence. The
regulator can also be disabled and bypassed at the user’s
discretion.
• f
• f
• V
• V
• T
• T
DDEXT
% Power Savings
CCLKNOM
CCLKRED
NOM
RED
DDINTNOM
DDINTRED
Figure 4
) supplied. While in hibernation, V
Power Savings Factor
is the duration running at f
is the duration running at f
=
-------------------- -
f
is the reduced core clock frequency
f
CCLKNOM
is the nominal core clock frequency
CCLKRED
is the reduced internal supply voltage
shows the typical external components
Figure 4. Voltage Regulator Circuit
is the nominal internal supply voltage
Preliminary Technical Data
=
×
(
1 Power Savings Factor
⎛
⎝
------------------------- -
V
V
–
DDINTNOM
DDINTRED
CCLKRED
⎞
⎠
CCLKNOM
2
×
⎛
⎝
DDEXT
------------ -
T
T
NOM
RED
⎞
⎠
) 100%
can still be
×