ADSP-BF561SKBCZ600 Analog Devices Inc, ADSP-BF561SKBCZ600 Datasheet - Page 24

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ADSP-BF561SKBCZ600

Manufacturer Part Number
ADSP-BF561SKBCZ600
Description
DSP Fixed-Point 16-Bit 600MHz 600MIPS 256-Pin CSP-BGA
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADSP-BF561SKBCZ600

Package
256CSP-BGA
Numeric And Arithmetic Format
Fixed-Point
Maximum Speed
600 MHz
Ram Size
32 KB
Device Million Instructions Per Second
600 MIPS
ADSP-BF561
Asynchronous Memory Read Cycle Timing
Table 14. Asynchronous Memory Read Cycle Timing
1
Output pins include AMS3–0, ABE3–0, ADDR25–2, AOE, ARE.
Parameter
Timing Requirements
t
t
t
t
Switching Characteristic
t
t
SDAT
HDAT
SARDY
HARDY
DO
HO
CLKOUT
AMSx
ABE1–0
ADDR19–1
ARE
ARDY
AOE
DATA15–0
DATA15–0 Setup Before CLKOUT
DATA15–0 Hold After CLKOUT
ARDY Setup Before CLKOUT
ARDY Hold After CLKOUT
Output Delay After CLKOUT
Output Hold After CLKOUT
2 CYCLES
SETUP
t
DO
Figure 8. Asynchronous Memory Read Cycle Timing
1
1
PROGRAMMED READ ACCESS
t
DO
Rev. PrC | Page 24 of 52 | April 2004
4 CYCLES
t
SARDY
BE, ADDRESS
t
HARDY
ACCESS EXTENDED
Min
2.1
0.8
4.0
0.0
0.8
3 CYCLES
Preliminary Technical Data
t
SARDY
t
t
HO
SDAT
READ
t
HARDY
Max
6.0
1 CYCLE
HOLD
t
HDAT
t
HO
Unit
ns
ns
ns
ns
ns
ns

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