ADSP-BF561SKBCZ600 Analog Devices Inc, ADSP-BF561SKBCZ600 Datasheet - Page 5

• Manufacturer Part Number: ADSP-BF561SKBCZ600
• Description: DSP Fixed-Point 16-Bit 600MHz 600MIPS 256-Pin CSP-BGA
• Manufacturer: Analog Devices Inc

Specifications of ADSP-BF561SKBCZ600

• Package: 256CSP-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 600 MHz
• Ram Size: 32 KB
• Device Million Instructions Per Second: 600 MIPS

Preliminary Technical Data
The fourth on-chip memory system is the L2 SRAM memory
array which provides 128K bytes of high speed SRAM operating
at one half the bandwidth of the core, and slightly longer latency
than the L1 memory banks. The L2 memory is a unified instruc-
tion and data memory and can hold any mixture of code and
data required by the system design. The Blackfin cores share a
dedicated low-latency 64-bit wide data path port into the L2
SRAM memory.
Each Blackfin core processor has its own set of core Memory
Mapped Registers (MMRs) but share the same system MMR
registers and 128 KB L2 SRAM memory.
External (Off-Chip) Memory
The ADSP-BF561 external memory is accessed via the External
Bus Interface Unit (EBIU). This interface provides a glueless
connection to up to four banks of synchronous DRAM
Topof last SDRAMpage
0xFFFFFFFF
0xFEB20000
0xFEB00000
0xFFE00000
0xFFC00000
0xFFB01000
0xFFB00000
0xFFA14000
0xFFA10000
0xFFA04000
0xFFA00000
0xEF004000
0xEF000000
0x2C000000
0xFF908000
0xFF904000
0xFF900000
0xFF808000
0xFF804000
0xFF800000
0x30000000
0x28000000
0x24000000
0x20000000
0x00000000
CO REM M RREG ISTERS
L1DATABANKASRAM /CACHE(16K)
L1SCRATCHPADSRAM(4K)
L1INSTRUCTIONSRAM /CACHE(16K)
L1INSTRUCTIONSRAM(16K)
L1DATABANKBSRAM /CACHE(16K)
L1DATABANKBSRAM(16K)
L1DATABANKASRAM(16K)
RESERVE D
RESERVE D
RESERVE D
RESERVE D
RESERVE D
COREAM EM O RYM AP
RESERVED
Rev. PrC | Page 5 of 52 | April 2004
SYSTEMM M RREG ISTERS
ASYNCM EM O RYBANK3
ASYNCM EM O RYBANK2
ASYNCM EM O RYBANK1
ASYNCM EM O RYBANK0
Figure 3. Memory Map
S DRAMBANK3
S DRAMBANK2
S DRAMBANK1
S DRAMBANK0
L2SRAM(128K)
RESERVED
RESERVED
RES ERVED
BO OTRO M
RESERVED
CO REM M RREGISTERS
L1DATABANKBSRAM /CACHE(16K)
L1DATABANKASRAM /CACHE(16K)
L1INSTRUCTIONSRAM /CACHE(16K)
L1INSTRUCTIONSRAM(16K)
RESE RVED
L1SCRATCHPADS RAM(4K)
RESE RVED
RESE RVED
RESE RVED
L1DATABANKBSRAM(16K)
RESE RVED
L1DATABANKASRAM(16K)
COREBM EM O RYM AP
RESE RVED
(SDRAM) as well as up to four banks of asynchronous memory
devices including flash, EPROM, ROM, SRAM, and memory
mapped I/O devices.
The PC133-compliant SDRAM controller can be programmed
to interface to up to four banks of SDRAM, with each bank con-
taining between 16M bytes and 128M bytes providing access to
up to 512M bytes of SDRAM. Each bank is independently pro-
grammable and is contiguous with adjacent banks regardless of
the sizes of the different banks or their placement. This allows
flexible configuration and upgradability of system memory
while allowing the core to view all SDRAM as a single, contigu-
ous, physical address space.
The asynchronous memory controller can also be programmed
to control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a
0xFF800000
0xFF701000
0xFF700000
0xFF614000
0xFF610000
0xFF604000
0xFF600000
0xFF508000
0xFF504000
0xFF500000
0xFF408000
0xFF404000
0xFF400000
EX TERNALM EM O RY
INTERNALM EM O RY
ADSP-BF561