ADSP-BF561SKBCZ600 Analog Devices Inc, ADSP-BF561SKBCZ600 Datasheet - Page 6

• Manufacturer Part Number: ADSP-BF561SKBCZ600
• Description: DSP Fixed-Point 16-Bit 600MHz 600MIPS 256-Pin CSP-BGA
• Manufacturer: Analog Devices Inc

Specifications of ADSP-BF561SKBCZ600

• Package: 256CSP-BGA
• Numeric And Arithmetic Format: Fixed-Point
• Maximum Speed: 600 MHz
• Ram Size: 32 KB
• Device Million Instructions Per Second: 600 MIPS

ADSP-BF561
64M-byte segment regardless of the size of the devices used so
that these banks will only be contiguous if fully populated with
64M bytes of memory.
I/O Memory Space
Blackfin processors do not define a separate I/O space. All
resources are mapped through the flat 32-bit address space. On-
chip I/O devices have their control registers mapped into mem-
ory-mapped registers (MMRs) at addresses near the top of the
4G-byte address space. These are separated into two smaller
blocks, one which contains the control MMRs for all core func-
tions, and the other which contains the registers needed for
setup and control of the on-chip peripherals outside of the core.
The core MMRs are accessible only by the core and only in
supervisor mode and appear as reserved space by on-chip
peripherals. The system MMRs are accessible by the core in
supervisor mode and can be mapped as either visible or reserved
to other devices, depending on the system protection model
desired.
Booting
The ADSP-BF561 contains a small boot kernel, which config-
ures the appropriate peripheral for booting. If the ADSP-BF561
is configured to boot from boot ROM memory space, the pro-
cessor starts executing from the on-chip boot ROM.
Event Handling
The event controller on the ADSP-BF561 handles all asynchro-
nous and synchronous events to the processor. The ADSP-
BF561 provides event handling that supports both nesting and
prioritization. Nesting allows multiple event service routines to
be active simultaneously. Prioritization ensures that servicing of
a higher-priority event takes precedence over servicing of a
lower-priority event. The controller provides support for five
different types of events:
Each event has an associated register to hold the return address
and an associated return-from-event instruction. When an
event is triggered, the state of the processor is saved on the
supervisor stack.
• Emulation – An emulation event causes the processor to
• Reset – This event resets the processor.
• Non-Maskable Interrupt (NMI) – The NMI event can be
• Exceptions – Events that occur synchronously to program
• Interrupts – Events that occur asynchronously to program
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shut
down of the system.
flow, i.e., the exception will be taken before the instruction
is allowed to complete. Conditions such as data alignment
violations, undefined instructions, etc. cause exceptions.
flow. They are caused by timers, peripherals, input pins,
and an explicit software instruction.
Rev. PrC | Page 6 of 52 | April 2004
The ADSP-BF561 event controller consists of two stages, the
Core Event Controller (CEC) and the System Interrupt Control-
ler (SIC). The Core Event Controller works with the System
Interrupt Controller to prioritize and control all system events.
Conceptually, interrupts from the peripherals enter into the
SIC, and are then routed directly into the general-purpose inter-
rupts of the CEC.
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest-priority inter-
rupts (IVG15–14) are recommended to be reserved for software
interrupt handlers, leaving seven prioritized interrupt inputs to
support the peripherals of the ADSP-BF561.
the inputs to the CEC, identifies their names in the Event Vector
Table (EVT), and lists their priorities.
Table 1. Core Event Controller (CEC)
System Interrupt Controller (SIC)
The System Interrupt Controller provides the mapping and
routing of events from the many peripheral interrupt sources, to
the prioritized general-purpose interrupt inputs of the CEC.
Although the ADSP-BF561 provides a default mapping, the user
can alter the mappings and priorities of interrupt events by writ-
ing the appropriate values into the Interrupt Assignment
Registers (IAR).
the default mappings into the CEC.
Priority
(0 is Highest)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Table 2
Preliminary Technical Data
General Interrupt 10
General Interrupt 11
General Interrupt 12
General Interrupt 13
General Interrupt 14
General Interrupt 15
Event Class
Emulation/Test
Reset
Non-Maskable
Exceptions
Global Enable
Hardware Error
Core Timer
General Interrupt 7
General Interrupt 8
General Interrupt 9
describes the inputs into the SIC and
Table 1
EVT Entry
EMU
RST
NMI
EVX
-
IVHW
IVTMR
IVG7
IVG8
IVG9
IVG10
IVG11
IVG12
IVG13
IVG14
IVG15
describes