PEB20256E-V21 Infineon Technologies, PEB20256E-V21 Datasheet - Page 192
![IC CONTROLLER INTERFACE 388-BGA](/photos/6/98/69826/peb20256e-v21_sml.jpg)
PEB20256E-V21
Manufacturer Part Number
PEB20256E-V21
Description
IC CONTROLLER INTERFACE 388-BGA
Manufacturer
Infineon Technologies
Datasheet
1.PEB20256E-V21.pdf
(232 pages)
Specifications of PEB20256E-V21
Function
Multichannel Network Interface Controller (MUNICH)
Interface
HDLC, PPP, Serial, TMA
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
200mA
Power (watts)
3W
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
388-BBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Circuits
-
Other names
PEB20256E-V21
PEB20256E-V21IN
PEB20256E-V21IN
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IF
Q8..Q0
Data Sheet
as LINT changes from an inactive to an active state the interrupt pin
INTA will be asserted.
Note: This bit does not clear by writing a ’1’. This bit is set as long as
0
1
Interrupt FIFO
This bit indicates that there is an interrupt vector stored in the internal
interrupt FIFO. The IF interrupt is available if the interrupt pin LINT is
switched to input mode (INTCTRL.ID = ’1’) and when the interrupt mask
GMASK.IF is set to ’0’.
Note: This bit does not clear by writing a ’1’. This bit is set as long as an
0
1
Interrupt Queue 8..0
On reads each bit flags one or more interrupt vectors that have been
written to the corresponding interrupt queue. If one of the bits is set and
the same bit is not masked in register GMASK, the interrupt pin INTA will
be asserted. A bit is cleared, when an ’1’ is written to the specific bit.
0
1
the interrupt pin LINT is asserted.
LINT not asserted.
LINT asserted.
interrupt vector is stored in the interrupt FIFO.
No Interrupt vector in interrupt FIFO.
Interrupt vector stored in internal interrupt FIFO.
No interrupt vector written.
Read: One or more interrupt vectors have been written to
interrupt queue.
Write: Clear bit
192
Register Description
PEB 20256 E
PEF 20256 E
04.2001
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