AT32UC3C1128C Atmel Corporation, AT32UC3C1128C Datasheet - Page 1151
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AT32UC3C1128C
Manufacturer Part Number
AT32UC3C1128C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C1128C
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
81
Ext Interrupts
100
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
36
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
19
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C1128C-AUR
Manufacturer:
ATMEL
Quantity:
870
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3C0128C PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
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37.6.1.4
37.6.2
37.6.2.1
32117C–AVR-08/11
Advanced Operation
Data Registers
Prescaler
Data to be converted is taken from two registers, one for each channel: Data Register 0 (DR0)
for channel A and Data Register 1 (DR1) for channel B.
Alternatively both samples to be converted can be written to DR0 in a single write cycle, in this
configuration the values for channel B and A are written to the upper and the lower half words of
DR0, respectively. This operation is possible only if the DAC Dual Data in Data Register A bit of
the Configuration register (CFR.DDA) is enabled.
While the field reserved for the data to be converted is 16 bits wide, only the 12 lower bits are
considered for conversion. In order to match the expected data alignment, rounded right and left
shifts are programmable within a separate register for each data channel.
A programmable prescaler generates a divided clock signal from the system clock. This signal is
then fed to the following DACIFB programmable counters, as shown on
The limitations described in the
when configuring these programmable counters.
In addition to these constraints, when both channels are in use with auto-refresh mode enabled,
the refresh rate should not be significantly higher than the sampling rate on the other channel as
this might cause unexpected behavior on the latter channel.
• The channel interval counter, which sets the minimum time interval between two samples, or
• The S/H refresh counter which, in refresh mode, counts a defined number of prescaled clock
• Trigger event timer counters for both channels which, in timer trigged mode, count a defined
in other words, the maximum sampling frequency (see CHI bitfield in the TCR register).
ticks (corresponding to the refresh time) before repeating the conversion of the last received
data (see CHRA and CHRB bitfields in the TCR register).
number of prescaled clock ticks before triggering a conversion (see the TRA and TRB
registers).
“Timing constraints”
paragraph must be taken into consideration
Figure
AT32UC3C
37-2:
1151
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