AT32UC3C1128C Atmel Corporation, AT32UC3C1128C Datasheet - Page 808

• Manufacturer Part Number: AT32UC3C1128C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C1128C

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 81
• Ext Interrupts: 100
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 19
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

30.6.7
30.6.8
32117C–AVR-08/11
Mono
Holding Registers
Figure 30-4. IISC Clocks Generation
When the Transmit Mono (TXMONO) in the Mode Register is set, data written to the left channel
is duplicated to the right output channel. In TDM mode with more than two channels, numbered
from 0, data written to the even-numbered channels is duplicated to the following odd-numbered
channel.
When the Receive Mono (RXMONO) in the Mode Register is set, data received from the left
channel is duplicated to the right channel. In TDM mode with more than two channels, num-
bered from 0, data received from the even-numbered channels is duplicated to the following
odd-numbered channel.
The IISC user interface includes a Receive Holding Register (RHR) and a Transmit Holding
Register (THR). RHR and THR are used to access audio samples for all audio channels.
When a new data word is available in the RHR register, the Receive Ready bit (RXRDY) in the
Status Register (SR) is set. Reading the RHR register will clear this bit.
A receive overrun condition occurs if a new data word becomes available before the previous
data word has been read from the RHR register. Then, the Receive Overrun bit in the Status
Register will be set and bit i of the RXORCH field in the Status Register is set, where i is the cur-
rent receive channel number.
When the THR register is empty, the Transmit Ready bit (TXRDY) in the Status Register (SR) is
set. Writing into the THR register will clear this bit.
A transmit underrun condition occurs if a new data word needs to be transmitted before it has
been written to the THR register. Then, the Transmit Underrun bit in the Status Register will be
MR.IMCKMODE
MR.MODE = SLAVE
ISCK pin input
IWS pin input
GCLK_IISC
CR.CKEN/CKDIS
0
1
enable
Clock
0
1
0
1
CR.CKEN/CKDIS
MR.IMCKMODE
enable
Clock
divider
Clock
divider
Clock
MR.IMCKFS
MR.DATALENGTH
MR.DATALENGTH
IMCK pin output
ISCK pin output
Internal
bit clock
Internal
word clock
IWS pin output
AT32UC3C
808