AT32UC3C1128C Atmel Corporation, AT32UC3C1128C Datasheet - Page 763

• Manufacturer Part Number: AT32UC3C1128C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C1128C

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 81
• Ext Interrupts: 100
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 36
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 19
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

29.5.5
29.5.6
29.6
29.6.1
29.6.1.1
32117C–AVR-08/11
Functional Description
Interrupts
Debug Operation
Channel Configuration
Bit timing
CANIF interrupt request line is connected to the interrupt controller. Using the CANIF interrupt
requires the interrupt controller to be programmed first.
All CAN channels are disabled when the CPU enters Debug mode. Communication in progress
is not stopped. Please refer to the On-Chip Debug chapter in the AVR32UC Technical Refer-
ence Manual, and the OCD Module Configuration section, for details.
Channel configuration is done via the Configuration Register (CANCFG). This register is not
write accessible once the channels have been enabled.
This section refers to chapter 8 (Bit timing requirements) of the CAN Specification.
The CAN bit rate is defined by the nominal bit time. Nominal bit time is divided into 4 time
segments.
Figure 29-2. Partition of the Bit Time
The duration of each time segment is divided into time quanta (TQ). The total number of TQ in a
bit time must be in the range [8..25].
The Time Quantum is a fixed unit of time derived from the GCLK_CANIF clock period:
Re-synchronization may lengthen or shorten the bit time, the upper bound is given by Synchroni-
zation Jump Width field in the Configuration Register (CANCFG.SJW).
The value of all previous parameters are defined in CANCFG register.
Table 29-2.
PHASE_SEG1
PROP_SEG
SYNC_SEG
Parameter
TQ = Prescaler x
CAN Parameter Settings
SYNC_SEG
[1..8]TQ
[1..8]TQ
Range
1
PROP_SEG
P
GCLK_CANIF
Nominal bit time
CANCFG field
PHS1 + 1
PRS + 1
= (CANCFG.PRES+1) x
-
PHASE_SEG1
Sample Point
PHASE_SEG2
P
GCLK_CANIF
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