AT32UC3C1256C Atmel Corporation, AT32UC3C1256C Datasheet - Page 1035

• Manufacturer Part Number: AT32UC3C1256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C1256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 81
• Ext Interrupts: 100
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 19
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

33.7.37
Name:
Access Type:
Offset:
Reset Value:
This register can only be written if the WPSWS2 and WPHWS2 bits are cleared in
1029.
• DTLI: Dead-Time PWMLx Output Inverted
• DTHI: Dead-Time PWMHx Output Inverted
• DTE: Dead-Time Generator Enable
• CES: Counter Event Selection
• CPOL: Channel Polarity
• CALG: Channel Alignment
32117C–AVR-08/11
CALG=0 (Left Alignment):
CALG=1 (Center Alignment):
31
23
15
7
-
-
-
-
0: The dead-time PWMLx output is not inverted.
1: The dead-time PWMLx output is inverted.
0: The dead-time PWMHx output is not inverted.
1: The dead-time PWMHx output is inverted.
0: The dead-time generator is disabled.
1: The dead-time generator is enabled.
The CES bit defines when the channel counter event occurs when the period is center aligned (CHIDx in the
Register 1” on page
0/1: The channel counter event occurs at the end of the PWM period.
0: The channel counter event occurs at the end of the PWM period.
1: The channel counter event occurs at the end of the PWM period and at half the PWM period.
0: The OCx output waveform (output from the comparator) starts at a low level.
1: The OCx output waveform (output from the comparator) starts at a high level.
0: The period is left aligned.
1: The period is center aligned.
Channel Mode Register
30
22
14
6
-
-
-
-
CMR
Read/Write
0x200 + [ch_num * 0x20]
0x00000000
1004).
29
21
13
5
-
-
-
-
28
20
12
4
-
-
-
-
27
19
11
3
-
-
-
DTLI
CES
26
18
10
2
-
”Write Protect Status Register” on page
CPRE
CPOL
DTHI
25
17
9
1
-
AT32UC3C
”Interrupt Status
CALG
DTE
24
16
8
0
-
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