AT32UC3C1256C Atmel Corporation, AT32UC3C1256C Datasheet - Page 977

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AT32UC3C1256C

Manufacturer Part Number
AT32UC3C1256C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT32UC3C1256C

Flash (kbytes)
256 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
81
Ext Interrupts
100
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
19
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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32117C–AVR-08/11
If a comparison unit is enabled (see
channel 0, in this case the comparison cannot match.
As soon as the fault protection is triggered on a channel, an interrupt (different from the interrupt
generated at the end of the PWM period) can be generated but only if it is enabled and not
masked. The interrupt is reset by reading the interrupt status register, even if the fault which has
caused the trigger of the fault protection is kept active.
• To prevent an unexpected activation of the status FSy bit in the FSR register, the FMODy bit
• To prevent an unexpected activation of the Fault Protection on the channel x, the FPEx[y] bit
can be written to one only if the FPOLy bit has been previously configured to its final value.
can be written to one only if the FPOLy bit has been previously configured to its final value.
Section 33.6.3 on page
986) and if a fault is triggered in the
AT32UC3C
977

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