AT32UC3C1256C Atmel Corporation, AT32UC3C1256C Datasheet - Page 496

• Manufacturer Part Number: AT32UC3C1256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C1256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 81
• Ext Interrupts: 100
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 19
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24.5.7
24.5.8
32117C–AVR-08/11
Receive Sub-module
Address Checking Sub-module
The pause quantum used in the generated frame depends on the trigger source for the frame as
follows:
After transmission, no interrupts are generated and the only statistics register that is incre-
mented is the pause frames transmitted register.
The receive sub-module checks for valid preamble, FCS, alignment and length, presents
received frames to the DMA interface and stores the frames destination address for use by the
address checking sub-module. If, during frame reception, the frame is found to be too long or
RX_ER is asserted, a bad frame indication is sent to the DMA interface. The DMA interface then
stops sending data to memory. At the end of frame reception, the receive sub-module indicates
to the DMA interface whether the frame is good or bad. The DMA interface recovers the current
receive buffer if the frame was bad. The receive sub-module signals the register sub-module to
increment the alignment error, the CRC (FCS) error, the short frame, long frame, jabber error,
the receive symbol error statistics and the length field mismatch statistics.
The enable bit for jumbo frames in the network configuration register allows the MACB to receive
jumbo frames of up to 10240 bytes in size. This operation does not form part of the IEEE802.3
specification and is disabled by default. When jumbo frames are enabled, frames received with a
frame size greater than 10240 bytes are discarded.
The address checking (or filter) sub-module indicates to the DMA interface which receive frames
should be copied to memory. Whether a frame is copied depends on what is enabled in the net-
work configuration register, the state of the external match pin, the contents of the specific
address and hash registers and the frame’s destination address. In this implementation of the
MACB, the frame’s source address is not checked. If bit 18 of the Network Configuration register
is not set, a frame is not copied to memory if the MACB is transmitting in half duplex mode at the
time a destination address is received. If bit 18 of the Network Configuration register is set,
frames can be received while transmitting in half-duplex mode.
Ethernet frames are transmitted a byte at a time, least significant bit first. The first six bytes (48
bits) of an Ethernet frame make up the destination address. The first bit of the destination
address, the LSB of the first byte of the frame, is the group/individual bit: this is One for multicast
addresses and Zero for unicast. The All Ones address is the broadcast address, and a special
case of multicast.
The MACB supports recognition of four specific addresses. Each specific address requires two
registers, specific address register bottom and specific address register top. Specific address
• fill of 00 to take the frame to minimum frame length
• valid FCS
1. If bit 11 is written with a one, the pause quantum comes from the transmit pause quan-
2. If bit 12 is written with a one, the pause quantum is zero.
3. If the tx_pause input is toggled and the tx_pause_zero input is held low until the next
4. If the tx_pause input is toggled and the tx_pause_zero input is held high until the next
tum register. The Transmit Pause Quantum register resets to a value of 0xFFFF giving
a maximum pause quantum as a default.
toggle, the pause quantum comes from the transmit pause quantum register.
toggle, the pause quantum is zero.
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