AT32UC3C1256C Atmel Corporation, AT32UC3C1256C Datasheet - Page 1150

• Manufacturer Part Number: AT32UC3C1256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C1256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 81
• Ext Interrupts: 100
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 19
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

37.6
37.6.1
37.6.1.1
37.6.1.2
37.6.1.3
32117C–AVR-08/11
Functional Description
Basic Operation
Output channels
Timing constraints
Starting a conversion
The output from the DAC can either be continuous to one pin (DAC channel A only), or fed to
two different pins using a sample and hold circuitry (S/H). With S/H these two outputs can act
independently and create two different analog signals, different in both voltage and frequency.
The two S/H outputs have individual data and conversion control registers.
The DAC output may be used as internal input signal to other peripherals, such as the Analog
Comparator or the ADC. Only the DAC internal output can be used as internal input, the S/H out-
puts can not be used as such. Note that in this internal routing mode, both S/H modules must be
deactivated in order to avoid disturbances on the internal channel.
Some timing constraints must be observed in order to make sure the S/H circuitry operates cor-
rectly. These are relative to the frequency of the peripheral clock of the DACIFB, as this will
affect the charging/discharging periods of the S/H circuitry. Not meeting these constraints will
result in reducing the accuracy of the DAC conversions.
The DAC sampling time is the time interval between two conversions. Without S/H operating,
this figure should be equal or greater than the DAC minimum sampling period (corresponding to
the DAC maximum sampling frequency). With S/H operating, this figure should be equal or
greater than 1.5 times the DAC minimum sampling period.
When the sampling frequency is too low, the S/H circuitry may let the output voltage drop signif-
icantly between two consecutive conversions. If enabled, the auto-refresh mode will
automatically repeat continuously the conversion of the last channel data. This allows maintain-
ing the voltage level on the S/H outputs, whenever the time elapsed between two data to be
converted is too long. The DAC refresh time is the time interval between two channel data
updates, it can not be smaller than the minimum sampling period.
The analog DAC startup time is non-null, therefore a waiting period of a few CLK_DACIFB clock
cycles must be observed before considering conversion of the first data.
Note that if S/H is enabled, the actual sampling period will be 1.5 times greater than the pro-
grammed sampling period.
Conversions are either performed upon writes to the data registers or triggered by an incoming
event (auto-trig mode). Both application software and the Peripheral DMA controller may write to
the data registers.
Using the Peripheral DMA Controller to write data to the DACIFB, together with an event input to
trigger conversions, gives the most accurate timing for conversions.
The Peripheral DMA Controller data transfer rate depends on the sampling frequency imposed
by the event line. The DACIFB sends a request to the Peripheral DMA Controller, and once the
request is granted (Peripheral DMA Controller acknowledge) the conversion is performed upon
reception of a trigger event.
AT32UC3C
1150