AT32UC3C1256C Atmel Corporation, AT32UC3C1256C Datasheet - Page 1104

• Manufacturer Part Number: AT32UC3C1256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C1256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 81
• Ext Interrupts: 100
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 19
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

36.4
36.5
36.5.1
36.5.2
36.5.3
36.5.4
36.5.5
32117C–AVR-08/11
I/O Lines Description
Product Dependencies
I/O Lines
Power Management
Clocks
Interrupts
Event System
Table 36-1.
The pins used for interfacing the ADCIFA may be multiplexed with the I/O Controller lines. The
programmer must first program the I/O Controller to assign the desired ADCIFA pins to their
peripheral function. If I/O lines of the ADCIFA are not used by the application, they can be used
for other purposes by the I/O Controller.
Not all ADCIFA inputs may be enabled. If an application requires only four channels, then only
four ADCIFA lines need to be assigned to ADCIFA inputs.
If the CPU enters a sleep mode that disables clocks used by the ADCIFA, the ADCIFA will stop
functioning and resume operation after the system wakes up from sleep mode. Before entering a
sleep mode where the clock to the ADCIFA is stopped, make sure the Analog-to-Digital Con-
verter cell is put in an inactive state. Refer to
The clock for the ADCIFA bus interface (CLK_ADICFA) is generated by the Power Manager.
This clock is turned on by default, and can be enabled and disabled in the Power Manager. It is
recommended to disable the ADCIFA before disabling the clock, to avoid freezing the ADCIFA in
an undefined state.
The ADCIFA interrupt line is connected to one of the internal sources of the Interrupt Controller
(INTC). Using the ADCIFA requires the INTC to be configured first.
The event controller provides the ADCIFA two trigger sources.
ADCREFN
ADCREFP
ADCREF0
ADCREF1
GNDANA
VDDANA
ADCINx
Name
I/O Lines Description
Description
ADC analog input
CFG.EXREF= 0: Normal operation, this pin is used to decouple ADC internal reference.
ADCREFP should be connected to a 100nF external decoupling capacitor.
CFG.EXREF= 1: Forcing reference using ADCREFP/ADCREFN differential pin pair voltage
Please refer to the
CFG.EXREF= 0: Normal operation, this pin is used to decouple ADC internal reference.
ADCREFN should be connected to a 100nF external decoupling capacitor.
CFG.EXREF= 1: Forcing reference using ADCREFP/ADCREFN differential pin pair voltage
Please refer to the
External reference input (with respect to analog ground) bypassed when CFG.RS is enabled
External reference input (with respect to analog ground) bypassed when CFG.RS is enabled
Analog power supply
Analog ground
Section 36.6.10
Section 36.6.10
for more information.
for more information.
Section 36.6.3
for more information.
AT32UC3C
1104