AT32UC3C1256C Atmel Corporation, AT32UC3C1256C Datasheet - Page 605

• Manufacturer Part Number: AT32UC3C1256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C1256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 81
• Ext Interrupts: 100
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 19
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 25-42. Slave Node Synchronization
32117C–AVR-08/11
Fractional Part (FP)
Clcok Divider (CD)
Synchro Counter
Baud Rate
LINIDRX
BRGR
BRGR
Clock
RXD
The time measurement is made by a 19-bit counter clocked by the sampling clock (see
25.6.1).
When the start bit of the Synch Field is detected the counter is reset. Then during the next 8
Tbits of the Synch Field, the counter is incremented. At the end of these 8 Tbits, the counter is
stopped. At this moment, the 16 most significant bits of the counter (value divided by 8) gives the
new clock divider (LINCD) and the 3 least significant bits of this value (the remainder) gives the
new fractional part (LINFP).
Once the Synch Field has been entirely received, the clock divider (LINCD) and the fractional
part (LINFP) are updated in the LIN Baud Rate register (LINBRR) with the computed values, if
the synchronization is not disabled by the bit SYNCDIS in the LIN Mode register (LINMR).
If after reception of the Synch Field, it appears that the computed baudrate deviation compared
to the initial baud rate is superior to the maximum tolerance FToI_Unsynch (+/- 15%) then the
clock divider (LINCD) and the fractional part (LINFP) are not updated and the error bit STE in the
Channel Status register CSR is set to 1.
If after reception of the Synch Field, it appears that the sampled Synch character is not equal to
0x55 then the clock divider (LINCD) and the fractional part (LINFP) are not updated, and the
error bit ISFE in the Channel Status register (CSR) is set to 1.
The bits LINSTE and LINISFE are reset by writing the bit RSTSTA at 1 in the Control register
(CR).
The accuracy of the synchronization depends on several parameters:
The following formula is used to compute the deviation of the slave bit rate relative to the master
bit rate after synchronization (F
• The nominal clock frequency (F
• The Baudrate
• The oversampling (Over=0 => 16X or Over=0 => 8X)
13 dominant bits (at 0)
Break Field
Baudrate_deviation
Initial CD
Initial FP
1 recessive bit
Delimiter
Break
(at 1)
Reset
SLAVE
Start
Bit
Nom
=
is the real slave node clock frequency).
1
⎛
⎝
) (the theoretical slave node clock frequency)
100
0
Synch Byte = 0x55
1
×
α [
-------------------------------------------------------------------------------------------- -
0
×
1
8
0
×
(
1
2 Over
–
0
8
000_0011_0001_0110_1101
Stop
×
Bit
0000_0110_0010_1101
101
F
Start
SLAVE
Bit
)
+ ]
ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7
β
×
Baudrate
AT32UC3C
⎞ %
⎠
Stop
Bit
Section
605