AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 1167

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AT32UC3C2256C

Manufacturer Part Number
AT32UC3C2256C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT32UC3C2256C

Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
45
Ext Interrupts
64
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
5
Twi (i2c)
2
Uart
4
Can
2
Lin
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
13
Input Capture Channels
6
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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37.7.11
Name:
Access Type:
Offset:
Reset Value:
• DSD: DAC Data Shift Direction
• DSV: DAC Data Shift Value
• DRN: DAC Data Rounding Enable
32117C–AVR-08/11
31
23
15
7
-
-
-
-
0: DAC input value to be converted is right aligned
1: DAC input value to be converted is left aligned.
The number of left or right shifts to be performed on the 16-bits data word before being fed to the DAC.
Up to 4 left shifts and 4 right shifts are possible. Set bit 3 to obtain a left shift, leave it de-asserted to perform a right shift.
0: No rounding
1: rounding with right shifting is enabled. This adds "1" to the LSB before the last right shift. This feature is enabled by default.
Data Register Control Channel B
30
22
14
6
-
-
-
-
DRCB
Read/Write
0x28
0x00000001
29
21
13
5
-
-
-
-
28
20
12
4
-
-
-
-
DSD
27
19
11
3
-
-
-
26
18
10
2
-
-
-
DSV
25
17
9
1
-
-
-
AT32UC3C
DRN
24
16
8
0
-
-
1167

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