AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 347

no-image

AT32UC3C2256C

Manufacturer Part Number
AT32UC3C2256C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT32UC3C2256C

Flash (kbytes)
256 Kbytes
Pin Count
64
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
45
Ext Interrupts
64
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
5
Twi (i2c)
2
Uart
4
Can
2
Lin
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
13
Input Capture Channels
6
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3C2256C-A2UR
Manufacturer:
Cirrus
Quantity:
48
Part Number:
AT32UC3C2256C-A2UR
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT32UC3C2256C-A2UT
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT32UC3C2256C-A2ZR
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT32UC3C2256C-A2ZT
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
AT32UC3C2256C-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
AT32UC3C2256C-Z
Manufacturer:
ATMEL
Quantity:
261
Part Number:
AT32UC3C2256C-Z2UR
Manufacturer:
ATMEL
Quantity:
93
19. SDRAM Controller (SDRAMC)
19.1
19.2
32117C–AVR-08/11
Features
Overview
Rev: 2.2.0.4
The SDRAM Controller (SDRAMC) extends the memory capabilities of a chip by providing the
interface to an external 16-bit SDRAM device. The page size supports ranges from 2048 to 8192
and the number of columns from 256 to 2048. It supports byte (8-bit) and halfword (16-bit)
accesses.
The SDRAMC supports a read or write burst length of one location. It keeps track of the active
row in each bank, thus maximizing SDRAM performance, e.g., the application may be placed in
one bank and data in the other banks. So as to optimize performance, it is advisable to avoid
accessing different rows in the same bank.
The SDRAMC supports a CAS latency of one, two, or three and optimizes the read access
depending on the frequency.
The different modes available (self refresh, power-down, and deep power-down modes) mini-
mize power consumption on the SDRAM device.
128-Mbytes address space
Numerous configurations supported
Programming facilities
Energy-saving capabilities
Error detection
SDRAM power-up initialization by software
CAS latency of one, two, and three supported
Auto Precharge command not used
– 2K, 4K, 8K row address memory parts
– SDRAM with two or four internal banks
– SDRAM with 16-bit data path
– Word, halfword, byte access
– Automatic page break when memory boundary has been reached
– Multibank ping-pong access
– Timing parameters specified by software
– Automatic refresh operation, refresh rate is programmable
– Automatic update of DS, TCR and PASR parameters (mobile SDRAM devices)
– Self-refresh, power-down, and deep power-down modes supported
– Supports mobile SDRAM devices
– Refresh error interrupt
AT32UC3C
347

Related parts for AT32UC3C2256C