AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 349

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.5
19.5.1
Figure 19-2. SDRAM Controller Connections to SDRAM Devices: 16-bit Data Bus Width
19.5.2
32117C–AVR-08/11
Application Example
Hardware Interface
Software Interface
Controller
SDRAM
SDRAMC_A[0-12]
DQM[0-1]
SDCKE
D0-D31
SDWE
SDCK
SDCS
RAS
CAS
BA0
BA1
Table 19-1.
Figure 19-2 on page 349
bus width. It is important to note that this example is given for a direct connection of the devices
to the SDRAMC, without External Bus Interface or I/O Controller multiplexing.
The SDRAM address space is organized into banks, rows, and columns. The SDRAMC allows
mapping different memory types according to the values set in the SDRAMC Configuration Reg-
ister (CR).
The SDRAMC’s function is to make the SDRAM device access protocol transparent to the user.
Table 19-2 on page 350
ping seen by the user in correlation with the device structure. Various configurations are
illustrated.
Name
DQM[1:0]
SDRAMC_A[12:0]
D[15:0]
I/O Lines Description
DQM0
D0-D7
D0-D7
CS
CLK
CKE
WE
RAS
CAS
DQM
SDRAM
2Mx8
Description
Data Mask Enable Signals
Address Bus
Data Bus
to
A0-A9 A11
shows an example of SDRAM device connection using a 16-bit data
Table 19-4 on page 350
BA0
BA1
A10
SDRAMC_A10
BA1
BA0
illustrate the SDRAM device memory map-
D8-D15
DQM1
D0-D7
CS
CLK
CKE
WE
RAS
CAS
DQM
SDRAM
2Mx8
Type
Output
Output
Input/Output
A0-A9 A11
A10
BA0
BA1
SDRAMC_A10
BA1
BA0
AT32UC3C
Active Level
High
349