AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 514

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24.7.5
Name:
Access Type:
Offset:
Reset Value:
This register points to the entry in the receive buffer queue (descriptor list) currently being used. It is written with the start
location of the receive buffer descriptor list. The lower order bits increment as buffers are used up and wrap to their original
values after either 1024 buffers or when the wrap bit of the entry is set.
Reading this register returns the location of the descriptor currently being accessed. This value is incremented as buffers
are used. User should not use this register to determine where to remove received frames from the queue as it constantly
changes when new frames are received. User should instead use the buffer descriptor queue checking the used bits.
Receive buffer writes can be bursts of two words and, as with transmit buffer reads, it is recommended that bit 2 is always
written to zero to prevent a burst crossing a 1K boundary, in violation of the System Bus specification.
• ADDR:
32117C–AVR-08/11
31
23
15
7
Write this field to set the start address of the receive queue.
Read this field to get the address of the current buffer being used.
Receive Buffer Queue Pointer Address
Receive Buffer Queue Pointer Register
30
22
14
6
RBQP
Read/Write
0x18
0x00000000
29
21
13
5
ADDR[5:0]
28
20
12
4
ADDR[29:22]
ADDR[21:14]
ADDR[13:6]
27
19
11
3
26
18
10
2
25
17
9
1
-
AT32UC3C
24
16
8
0
-
514