AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 771

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

29.6.5
32117C–AVR-08/11
Channel Interrupts
ID received:
IDT:
IDM:
Comparison:
Accepted:
The filtering process scans each MOb enabled and configured for reception, from MOb 0, in
order to find the MOb that matches the conditions. The first MOb to match is selected for storing
the message once received successfully. If no MOb matches, the message is discarded.
There are several sources of interrupts and user can mask each of them. Some sources are
grouped into a single interrupt request line. There are 5 interrupt request lines per channel.
The CANIMR and MOBIMR are used for masking interrupts. These registers are read-only. In
order to set or clear interrupt mask bits, user must write to the following registers:
To acknowledge an interrupt request, user must clear the corresponding bit in the corresponding
status register (CANISR, MTXISR or MRXISR). To clear status bits, user must access the fol-
lowing write-only registers:
For each MOb, the bits TXOK and RXOK are also accessible in MOBSCR register for clear
access and MOBSR register for read access.
• Wake-up interrupt: Wake-up condition detected
• Error interrupt: Any CAN error detected during a communication
• Bus off interrupt: The CAN protocol engine entered in bus off state
• Took interrupt: At least one MOb completed a transmission
• Waxed interrupt: At least one MOb completed a reception
• CANIER / MOBIER: Writing a bit to one sets the corresponding bit in CANIMR / MOBIMR.
• CANIDR / MOBIDR: Writing a bit to one clears the corresponding bit in CANIMR / MOBIMR.
• CANISCR / MTXISCR / MRXISCR: Writing a bit to one clears the corresponding bit in
Writing a bit to 0 has no effect.
Writing a bit to 0 has no effect.
CANISR / MTXISR / MRXISR. Writing a bit to 0 has no effect.
000.0010.1001 b
000.0010.1010 b
111.1111.0000 b
111.1111.- - - - b
Y
000.0010.1001 b
000.0100.1000 b
111.1111.0000 b
111.1001.- - - - b
N
AT32UC3C
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