AT32UC3C2256C Atmel Corporation, AT32UC3C2256C Datasheet - Page 804

• Manufacturer Part Number: AT32UC3C2256C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C2256C

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 45
• Ext Interrupts: 64
• Usb Transceiver: 1
• Quadrature Decoder Channels: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 5
• Twi (i2c): 2
• Uart: 4
• Can: 2
• Lin: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 3
• Output Compare Channels: 13
• Input Capture Channels: 6
• Pwm Channels: 14
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

30.5.3
30.5.4
30.5.5
30.5.6
30.6
30.6.1
30.6.2
32117C–AVR-08/11
Functional Description
Clocks
DMA
Interrupts
Debug Operation
Initialization
Basic Operation
The clock for the IISC bus interface (CLK_IISC) is generated by the Power Manager. This clock
is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the
IISC before disabling the clock, to avoid freezing the IISC in an undefined state.
One of the generic clocks is connected to the IISC. The generic clock (GCLK_IISC) can be set to
a wide range of frequencies and clock sources. The GCLK_IISC must be enabled and config-
ured before use. Refer to the module configuration section for details on the GCLK_IISC used
for the IISC. The frequency for this clock has to be set as described in Table.
The IISC DMA handshake interfaces are connected to the Peripheral DMA Controller. Using the
IISC DMA functionality requires the Peripheral DMA Controller to be programmed first.
The IISC interrupt line is connected to the Interrupt Controller. Using the IISC interrupt requires
the Interrupt Controller to be programmed first.
When an external debugger forces the CPU into debug mode, the IISC continues normal opera-
tion. If this module is configured in a way that requires it to be periodically serviced by the CPU
through interrupt requests or similar, improper operation or data loss may result during
debugging.
The IISC features a Receiver, a Transmitter, and, for Master and Controller modes, a Clock
Generator. Receiver and Transmitter share the same Serial Clock and Word Select.
Before enabling the IISC, the chosen configuration must be written to the Mode Register (MR).
The IMCKMODE, MODE, FORMAT, and DATALENGTH fields in the MR register must be writ-
ten. If FORMAT is configured in one of the TDM formats, then the NBCHAN and TDMFS fields
must also be written. If the IMCKMODE field is written as one, then the IMCKFS field should be
written with the chosen ratio, as described in
eration” on page
Once the Mode Register has been written, the IISC Clock Generator, Receiver, and Transmitter
can be enabled by writing a one to the CKEN, RXEN, and TXEN bits in the Control Register
(CR). The Clock Generator can be enabled alone, in Controller Mode, to output clocks to the
IMCK, ISCK, and IWS pins. The Clock Generator must also be enabled if the Receiver or the
Transmitter is enabled.
The Clock Generator, Receiver, and Transmitter can be disabled independently by writing a one
to CR.CXDIS, CR.RXDIS and/or CR.TXDIS respectively. Once requested to stop, they will only
stop when the transmission of the pending frame transmission will be completed.
The Receiver can be operated by reading the Receiver Holding Register (RHR), whenever the
Receive Ready (RXRDY) bit in the Status Register (SR) is set. Successive values read from
RHR will correspond to the samples from the left and right audio channels, or from channels 0 to
MR.NBCHAN in TDM mode, for the successive frames.
806.
Section 30.6.6 ”Serial Clock and Word Select Gen-
AT32UC3C
804